EP80579 Datasheet, PDF (316/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
12.4
12.4.1
12.4.2
The hardware interlock of the suspend function will guarantee that the channel will not
proceed beyond the current chain descriptor until the Suspend bit has been cleared in
the CCR, and the Channel Resume function will guarantee that the current chain
descriptor will be re-read to retrieve the modified NDAR/NDUAR value pointing to the
spliced chain descriptor. The channel will resume execution with the head of the spliced
linked list, and will traverse that linked list back to its original list of chain descriptors.
The channel must refrain from updating CDAR/CDUAR from NDAR/NDUAR in addition to
dropping the returned data. Were the channel to update its CDAR/CDUAR values, it
would “skip” the entire spliced chain in response to Channel Resume, because software
would have spliced in the new descriptor chain at a position “behind” the new value for
CDAR/CDUAR in the original chain.
Transfer Types
The EDMA controller is optimized to perform high throughput data transfers between
local memory locations, and from local memory to I/O subsystem memory. Supported
transfer types are summarized in the following subsections.
Local Memory to Local Memory
The local memory to local memory transfer will move blocks of data specified by
descriptors from one region in main memory to another. The channel control hardware
will issue read cycles to the local memory interface using an incrementing or
decrementing source address, and place the retrieved data into a channel buffer. It will
then issue write cycles back to the memory interface using an incrementing or constant
destination address. Each EDMA channel supports pipelining making it possible for a
single channel to have multiple read and write cycles active at the same time.
All read requests to memory are a full cache-line in length (64 B), so the EDMA channel
must discard data as needed to realign the initial read in a transfer to the alignment
specified by the source address. The number of cache-line reads issued by the
controller in any given internal arbitration cycle is dependent upon the number of
available cache-line spaces in the data queue, and upon the configuration of the
inbound/outbound arbiter, but is limited to a maximum of two cache-line requests.
All write requests to memory are also a full cache-line in length, although not all bytes
must be enabled for every write. The EDMA channel is responsible for translating the
alignment specified by the destination address registers and the destination alignment
bit in DCR into a corresponding set of byte enables for the initial write in a transfer.
Once the initial alignment has been enforced, the rest of the transfer on behalf of any
given descriptor is contiguous.
Local Memory to I/O Subsystem Memory
The local memory to I/O memory transfer will move blocks of data specified by chain
descriptors from a source region in main memory to a destination region in the I/O
subsystem. The channel control hardware will issue read cycles to the local memory
interface using an incrementing or decrementing source address, and place the
retrieved data into a channel buffer. It will then issue write cycles to the I/O subsystem
using an incrementing or constant destination address. Each EDMA channel supports
pipelining for this transfer type as well, thus multiple read and write requests may be
outstanding from the same EDMA channel at any given time during a block transfer.
All read and write requests are full cache-line size (64 B), irrespective of alignment and
length specified in the descriptors; it is up to the EDMA channel to discard read data
and calculate write byte enables to enforce the descriptor alignment specified.
Intel^® EP80579 Integrated Processor Product Line Datasheet
316
August 2009
Order Number: 320066-003US