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Intel^® EP80579 Integrated Processor
Table 33-37. SIW_SERIRQ Sampling Periods (Sheet 2 of 2)
SIW_SERIRQ PERIOD
12
13
14
15
16
SIGNAL SAMPLED
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
# OF CLOCKS PAST START
35
38
41
44
47
SIW_SERIRQ Period 14 is used to transfer IRQ13. Logical devices 4 (Serial Port 1), 5
(Serial Port 2) and 6 (WDT) shall have IRQ13 as a choice for their primary interrupt.
33.7.1.3
Stop Cycle Control
Once all IRQ/Data Frames have completed the Host Controller terminates SIW_SERIRQ
activity by initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame.
A Stop Frame is indicated when the SIW_SERIRQ is low for two or three clocks. If the
Stop Frame’s low time is two clocks then the next SIW_SERIRQ Cycle’s sampled mode
is the Quiet mode; and any SIW_SERIRQ device may initiate a Start Frame in the
second clock or more after the rising edge of the Stop Frame’s pulse. If the Stop
Frame’s low time is three clocks then the next SIW_SERIRQ Cycle’s sampled mode is
the Continuous mode; and only the Host Controller may initiate a Start Frame in the
second clock or more after the rising edge of the Stop Frame’s pulse.
33.7.1.4
Latency
Latency for IRQ/Data updates over the SIW_SERIRQ bus in bridge-less systems with
the minimum Host supported IRQ/Data Frames of seventeen, ranges up to 96 clocks
(2.88 µs with a 33 MHz PCI Bus). If one or more PCI to PCI Bridge is added to a
system, the latency for IRQ/ Data updates from the secondary or tertiary buses are a
few clocks longer for synchronous buses, and approximately double for asynchronous
buses.
33.7.1.5
EOI/ISR Read Latency
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency.
IRQ latency could cause an EOI or ISR Read to precede an IRQ transition that it should
have followed. This could cause a system fault. The host interrupt controller is
responsible for ensuring that these latency issues are mitigated. The recommended
solution is to delay EOIs and ISR Reads to the interrupt controller by the same amount
as the SIW_SERIRQ Cycle latency in order to ensure that these events do not occur out
of order.
33.7.1.6
Reset and Initialization
The SIW_SERIRQ bus uses SIW_LRESET# as its reset signal. The SIW_SERIRQ pin is
tri-stated by all agents while SIW_LRESET# is active. With reset, SIW_SERIRQ Slaves
are put into the (continuous) IDLE mode. The Host Controller is responsible for starting
the initial SIW_SERIRQ Cycle to collect system’s IRQ/Data default values. The system
then follows with the Continuous/ Quiet mode protocol (Stop Frame pulse width) for
subsequent SIW_SERIRQ Cycles. It is Host Controller’s responsibility to provide the
default values to the Interrupt controller and other system logic before the first
SIW_SERIRQ Cycle is performed. For SIW_SERIRQ system suspend, insertion, or
removal application, the Host controller must be programmed into Continuous (IDLE)
mode first. This is to guarantee SIW_SERIRQ bus is in IDLE state before the system
configuration changes.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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