EP80579 Datasheet, PDF (1633/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 41-7. PTP Frame Identification
Field
Version
TOS
Length
ID
Flags/Frag Offset
TTL
Protocol
Header Checksum
Source Address
Dest Address
Source port
Dest port
Length
Checksum
Field
Size
1
1
2
2
2
1
1
2
4
4
2
2
2
2
L4
L2
0x45 (IPv4)
x
x
x
x
Not Present
x
0x11 (UDP)
x
x
x
UPD Header
0x013F
(EventPort type)
x
Not Present
x
x
PTP Header
See Table 41-4, “IEEE1588 Version 1 and IEEE1588-2008 PTP Message
Formats” on page 1628
User Defined
Not Present
Not Present
User defined
Match programmable
location against a
programmable value
to determine to
timestamp
41.5.3.3
Modes of Operation
The specific message detection mode for each channel can be configured. Table 41-8
documents the supported modes of operation.
Table 41-8. Timestamping Configurations
“Offset 0040h: TS_Ch_Control[0-7] -
Time Synchronization Channel
Control Register (Per Ethernet
Channel)” on page 1656
Version
[31]
Mode
[20:16
]
mm
[0]
ta
[1]
L2
L4
PTP
Version 1
0
ignore
0
0
No Yes
Yes
0
ignore
1
0
No Yes
Yes
0
ignore ignore
1
No Yes
Yes
1
0
ignore ignore No Yes
Yes
1
1
ignore ignore No Yes
Yes
Behavior
PTP
Version 2
Messages
Sync (Rx Only)
No
Delay_req (Tx Only)
Sync (Tx Only)
No
Delay_req (Rx Only)
Sync
No
Delay_req
Sync
No
Delay_req
No
All messages
Locked
Yes
Yes
No
Yes
No
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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