EP80579 Datasheet, PDF (419/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.37 Offset DEh: SKPD - Scratchpad Data Register
Table 16-39. Offset DEh: SKPD - Scratchpad Data Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: DEh
Offset End: DFh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 00
Bit Acronym
Bit Description
Sticky
SCRTCH
Scratchpad: These bits are simply Read/Write storage bits
that have no effect on the IMCH functionality. BIOS
typically programs this register to the revision ID of the
Memory Reference Code.
Bit Reset
Value
0000h
Bit Access
RW
16.1.1.38 Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register
Table 16-40. Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: F6h
Offset End: F6h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
SYSMMREN
NSIMMREN
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
System Memory MMR Enable:
0 = This BAR is hardwired to all zeros (effectively disabling
this memory space).
1 = The SM Memory Mapped Register space and
corresponding Base Address Register (B:D:F:R
0,0,0,14H) is visible. Section 16.1.1.9, “Offset 14h:
SMRBASE - System Memory RCOMP Base Address
Register”
NSI MMR Enable:
0 = The NSI Memory Mapped Register space is disabled,
and does not claim any memory. (THE NSIBAR
register is still read/write accessible.)
1 = The NSI Memory Mapped Register space is visible, and
memory mapped accesses are claimed and decoded
appropriately. (B:D:F:R 0,0,0,4CH) Section 16.1.1.12,
“Offset 4Ch: NSIBAR - Root Complex Block Address
Register”
Reserved.
Reserved
Reserved
Reserved
Reserved
Bit Reset
Value
0b
0b
0b
0b
0b
0b
0b
0b
Bit Access
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
419