EP80579 Datasheet, PDF (859/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.3.3.3 Offset 108h: PxFB[0-1] – Port [0-1] FIS Base Address Register
Table 23-58. Offset 108h: PxFB[0-1] – Port [0-1] FIS Base Address Register
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 108h, 188h
Offset End: 10Bh, 18Bh
Size: 32 bit
Default: Variable
Power Well: Core
Bit Range
31 : 08
07 : 00
Bit Acronym
Bit Description
Sticky
FB
Reserved
FIS Base Address (FB): Indicates the 32-bit base for
received FISes. This address must be 256-byte aligned as
indicated by bits 31:08 being read/write.
Note that these bits are not reset on a HBA reset.
Reserved
Bit Reset
Value
XX
00h
Bit Access
RW
RO
23.3.3.4 Offset 10Ch: PxFBU[0-1] – Port [0-1] FIS Base Address Upper 32-bits
Register
Table 23-59. Offset 10Ch: PxFBU[0-1] – Port [0-1] FIS Base Address Upper 32-bits Register
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 10Ch, 18Ch
Offset End: 10Fh, 18Fh
Size: 32 bit
Default: Variable
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
FBU
FIS Base Address Upper (FBU): Indicates the upper
32-bits for the received FIS base for this port.
Note that these bits are not reset on a HBA reset.
Sticky
Bit Reset
Value
Bit Access
Variable
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
859