EP80579 Datasheet, PDF (1014/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
CMIhas 44-bit addressing internally for both control and data structures. Address bits
63:44 [31:12] are hardwired to zero independent of the setting of this register. The
lower 12 address bits 43:32 [11:0] are fully read/write capable for software
compatibility and specification compliance.
Table 26-44. Offset 30h: CTRLDSSEGMENT - Control Data Structure Segment Register
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 30h
Offset End: 33h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :12
11 :00
Bit Acronym
Bit Description
Sticky
HC_UP
HC_LWR
Upper Address[63:44]: This 20-bit field is hard wired to
zero.
Upper Address[43:32]: This 12-bit field corresponds to
address bits 43:32 when forming a control data structure
address.
Bit Reset
Value
0h
0h
Bit Access
RO
RW
26.3.2.6
Offset 34h: PERIODICLISTBASE - Periodic Frame List Base Address
Register
This 32-bit register contains the beginning address of the Periodic Frame List in the
system memory. Since the host controller operates in 64-bit mode (as indicated by the
one in the 64-bit Addressing Capability field in the HCCSPARAMS register) (offset 08h,
bit 0), then the most significant 32 bits of every control data structure address comes
from the CTRLDSSEGMENT register. System software loads this register prior to
starting the schedule execution by the Host Controller. The memory structure
referenced by this physical memory pointer is assumed to be 4 Kbyte aligned. The
contents of this register are combined with the Frame Index Register (FRINDEX) to
enable the Host Controller to step through the Periodic Frame List in sequence.
Table 26-45. Offset 34h: PERIODICLISTBASE - Periodic Frame List Base Address Register
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 34h
Offset End: 37h
Size: 32 bit
Default: 00000XXXh
Power Well: Core
Bit Range
31 :12
11 :00
Bit Acronym
Bit Description
Sticky
HC_LOW
Reserved
Base Address (Low): These bits correspond to memory
address signals [31:12], respectively.
Reserved. Must be written as 0s. During runtime, the
value of these bits are undefined.
Bit Reset
Value
0h
XXXh
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1014
August 2009
Order Number: 320066-003US