EP80579 Datasheet, PDF (1181/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 33-17. Offset 02h: FCR - FIFO Control Register (Sheet 2 of 2)
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 02h
Offset End: 02h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
01
00
Bit Acronym
Bit Description
Sticky
RESETRF
TRFIFOE
Reset Receiver FIFO: When RESETRF is set to 1, the
receiver FIFO counter is reset to 0, effectively clearing
all the bytes in the FIFO. The DR bit in LSR is reset to 0.
All the error bits in the FIFO and the FIFOE bit in LSR
are cleared. Any error bits, OE, PE, FE or BI, that had
been set in LSR are still set. The receiver shift register is
not cleared. If IIR had been set to Received Data
Available, it is cleared. After the FIFO is cleared,
RESETRF is automatically reset to 0.
0 = Writing 0 has no effect
1 = The receiver FIFO is cleared (FIFO counter set to
0). After clearing, bit is automatically reset to 0
Transmit and Receive FIFO Enable: TRFIFOE
enables/disables the transmitter and receiver FIFOs.
When TRFIFOE = 1, both FIFOs are enabled (FIFO
Mode). When TRFIFOE = 0, the FIFOs are both disabled
(non-FIFO Mode). Writing a 0 to this bit clears all bytes
in both FIFOs. When changing from FIFO mode to non-
FIFO mode and vice versa, data is automatically cleared
from the FIFOs. This bit must be 1 when other bits in
this register are written or the other bits are not
programmed.
0 = FIFOs are disabled
1 = FIFOs are enabled
Bit Reset
Value
0b
0b
Bit Access
WO
WO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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