EP80579 Datasheet, PDF (1081/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.5.3
27.5.3.1
S0/C0, S0/C2, Entry/Exit Timings and Sequences
The timings associated with the C0-C2-C0, sequences are shown in the following
figures and tables.
C0→C2→C0 Timings and Diagram
Figure 27-1. C0→C2→C0 Entry/Exit Timings
CPU I/F
Signals
S0/C0 State
Unlatched _Latched
t1
S0/C2 State
STPCLK#
CPU FSB
M-I Link
t2a
t4b
SG
SG ^{Go- Ack-}
t2b
C2 C2
t3a
t4a
Go- Ack-
C0 C0
t3b
Break
Event
S0/C0 State
Unlatched
t6
t5
Note:
In Figure 27-1, the M-I Link must be labeled as “NSI” and the “SG” message on NSI
must be “Req-C2”
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1081