EP80579 Datasheet, PDF (1093/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 27-37. Write-Only Registers with Read Paths in Alternate Access Mode (Sheet 2 of 2)
Restore Data
Restore Data
I/O # of
Addr Reads
Access
Data
I/O
Addr
# of
Reads
Access
Data
1
PIC ICW2 of Master
controller
1
DMA Chan 4-7
Command²
2
PIC ICW3 of Master
controller
2
DMA Chan 4-7 Request
3
PIC ICW4 of Master
controller
4
PIC OCW1 of Master
controller¹
D0h
6
3
DMA Chan 4 Mode:
Bits(1:0) = “00”
4
DMA Chan 5 Mode:
Bits(1:0) = “01”
5
PIC OCW2 of Master
controller
5
DMA Chan 6 Mode:
Bits(1:0) = “10”
20h
12
6
PIC OCW3 of Master
controller
7
PIC ICW2 of Slave
controller
6
DMA Chan 7 Mode:
Bits(1:0) = “11”.
8
PIC ICW3 of Slave
controller
9
PIC ICW4 of Slave
controller
10
PIC OCW1 of Slave
controller¹
11
PIC OCW2 of Slave
controller
12
PIC OCW3 of Slave
controller
Notes:
1.
The OCW1 register must be read before entering Alternate Access Mode.
2.
Bits 5, 3, 1, and 0 return 0.
3.
The additional write-only registers are described in their respective sections.
27.9.2
PIC Reserved Bits
Many bits within the PIC are reserved, and must have certain values written in order for
the PIC to operate properly. Therefore, there is no need to return these values in
alternate (ALT) access mode. When reading PIC registers from 20h and A0h, the
reserved bits shall return the values listed in Table 27-38.
Table 27-38. PIC Reserved Bits Return Values
PIC Reserved Bits
ICW2(2:0)
ICW4(7:5)
ICW4(3:2)
ICW4(0)
OCW2(4:3)
OCW3(7)
OCW3(5)
OCW3(4:3)
Value Returned
000
000
00
0
00
0
Reflects bit 6
01
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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