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4. Asynchronous DMA memory accesses may be interleaved at any point with the
periodic DMA memory accesses on the IMCH/IICH link.
5. When writing back the qTD information after clearing the Active bit, the EHCI
Specification does not require that the C_Page field is written. However, due to
byte-granular write control, the EHC does write to this field, and the value is not
necessarily the final or incremented C_Page value.
26.6.2
Asynchronous List Execution
The Asynchronous DMA engine contains buffering for two control structures (two
transactions). By implementing two entries, the EHC is able to pipeline the memory
accesses for the next transaction while executing the current transaction on the USB
ports.
26.6.2.1
Read Policies for Asynchronous DMA
The Asynchronous DMA engine performs reads for the following structures:
Table 26-51. Asynchronous DMA Engine Reads
Memory Structure
qTD
Queue Head
Out Data
Size
(DWORDS)
13
17
Up to 129
Comments
Only the 64-bit addressing format is supported.
Only the 64-bit addressing format is supported.
Large read requests are broken down in to smaller aligned read
requests based on the setting of the Read Request Maximum
Length field.
Asynchronous DMA read policies:
1. The EHC Asynchronous DMA Engine (ADE) does not generate accesses to main
memory unless all four of the following conditions are met. (The ADE may be active
when the periodic schedule is actively executed, unlike the description in the EHCI
Specification; since the EHC contains independent DMA engines, the ADE may
perform memory accesses interleaved with the PDE accesses.)
a. The HCHalted bit is 0 (memory space, offset 24h, bit 12). Software clears this
bit indirectly by setting the RUN/STOP bit to 1.
b. The Asynchronous Schedule Status bit is 1 (memory space, offset 24h, bit 14).
Software sets this bit indirectly by setting the Asynchronous Schedule Enable
Bit to 1.
c. The Bus Master Enable bit is 1 (configuration space, offset 04h, bit 2).
d. The ADE is not sleeping due to the detection of an empty schedule. There is not
one single bit that indicates this state. However, the sleeping state is entered
when the Queue Head with the H bit set is encountered when the Reclamation
bit in the USB 2.0 Status register is 0.
2. Once the above conditions are met, the ADE immediately begins reading the Queue
Head to which the Current Asynchronous List Address Register points. Delays
within the arbitration and datapath are possible before the first read request is
presented on the IMCH/IICH link.
3. If prefetching is disabled, the ADE will perform transactions serially (no pipelining).
4. The ADE fetches structures in the asynchronous list until all information (including
data) is available to run one USB transaction before beginning to fetch the
structures for a pipelined transaction.
5. The ADE will not generate any control structure reads if both of the transaction
buffers are occupied. Data reads are the only read requests that will be generated
by the ADE in this case.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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