EP80579 Datasheet, PDF (1096/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.10.6
VRMPWROK
The VRMPWROK signal is generated by the processor’s VRM. It indicates that the
voltage outputs from the VRM are on and within spec.
27.11 Legacy Power Management Theory of Operation
27.11.1
Overview
Instead of relying on ACPI software, legacy power management uses BIOS and various
hardware mechanisms. The scheme relies on the concept of detecting when individual
subsystems are idle, detecting when the whole system is idle, and detecting accesses
are attempted to idle subsystems.
However, the OS is assumed to at least be APM enabled. Without APM calls, there is no
quick way to know when the system is idle between keystrokes. CMI does not support
burst modes.
27.11.2
APM Power Management
CMI has a timer, when enabled by the 1MIN_EN bit in the SMI Control and Enable
register, generates a periodic SMI# once per minute. There is also an option to have it
generate the SMI# once per 32, 16, or 8 seconds.The SMI handler can check for
system activity by reading the DEVTRAP_STS register. If none of the system bits are
set, the SMI handler can increment a software counter.
If there is activity, the various bits in the DEVTRAP_STS register will be set. Software
clears the bits by writing a 1 to the bit position.
The DEVTRAP_STS register allows for monitoring of various internal devices or Super I/
O devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions
on PCI or LPC. Other PCI activity can be monitored by checking the PCI Interrupts.
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Intel^® EP80579 Integrated Processor Product Line Datasheet
1096
August 2009
Order Number: 320066-003US