EP80579 Datasheet, PDF (822/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.1.1.5 PI - Programming Interface Register
Table 23-6. Programming Interface, DID and CC.SCC Register Value Definitions
Input Parameters
Resulting Values
MAP.SMS:
00 - Select IDE
01 - Select AHCI
10 - Reserved
11 - Reserved
00b
01b
10b
11b
MAP.MV
00b
00b
00b
00b
CC.SCC
01h
(IDE)
06h
(SATA)
Illegal^b
Illegal
PI
8Ah^a
(RW)
01h
(RO)
Illegal
Illegal
DID
5028h
5029h
Illegal
Illegal
a. PI register bits 2 and 0 are write-able at all times when MAP.MV=00h (so the value of this
field may be 8Ah, 8Bh, 8Dh, or 8Fh), although the write only affects the SATA controller's
operation when CC.SCC is 01h. If PI is written while CC.SCC is 04h, the value shown will
not be 8Ah when CC.SCC is changed from 04h to 01h, but rather the value of the last write
to PI. BIOS must always check and set PI to the desired mode of operation (legacy or
native) when CC.SCC is 01h.
b. "Illegal" means that SW must not program this combination otherwise the results are
undefined.
23.1.1.5.1 Programming Interface when CC.SCC = “01h”
Table 23-7. Programming Interface when CC.SCC = “01h”
Bit
Type Reset
Description
7
RO
6:4
RO
3
RO
1
Indicates the SATA Controller supports bus master operation.
0
Reserved
Secondary Mode Native Capable (SNC): Indicates that the secondary
1
controller supports both legacy and native modes.
Secondary Mode Native Enable (SNE): Determines the mode that the
secondary channel is operating in. ‘0’ corresponds to 'compatibility', ‘1’ means
PCI native. If this bit is set by SW, then the PNE bit must also be set by SW.
2
RW
0
While in theory these bits can be programmed separately, such a configuration
is not supported by today’s software and is not supported by this hardware.
Primary Mode Native Capable (PNC): Indicates that the primary controller
1
RO
1
supports both legacy and native modes.
Primary Mode Native Enable (PNE): Determines the mode that the primary
channel is operating in. ‘0’ corresponds to 'compatibility', ‘1’ means PCI native.
If this bit is set by SW, then the SNE bit must also be set by SW. While in theory
0
RW
0
these bits can be programmed separately, such a configuration is not supported
by today’s software and is not supported by this hardware.
Intel^® EP80579 Integrated Processor Product Line Datasheet
822
August 2009
Order Number: 320066-003US