EP80579 Datasheet, PDF (770/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
20.2.1.5 Offset 08h: DMA_COMMAND - DMA Command Register
Table 20-8. Offset 08h: DMA_COMMAND - DMA Command Register
Description:
View: IA F 1^a Base Address: 0000h (IO)
Offset Start: 08h
Offset End: 08h
View: IA F 1 Base Address: 0000h (IO)
Offset Start: 18h
Offset End: 18h
View: IA F 2^b Base Address: 0000h (IO)
Offset Start: D0h
Offset End: D0h
View: IA F 2 Base Address: 0000h (IO)
Offset Start: D1h
Offset End: D1h
Size: 8 bit
Default: 000X0X00b
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
07 : 05
04
03
02
01 : 00
Reserved
DMAARB
Reserved
DMACGEN
Reserved
Reserved. Software must always write 0 to these bits.
DMA Group Arbitration Priority: Each channel group is
individually assigned either fixed or rotating arbitration
priority. At reset, each group is initialized in fixed priority.
0 = Assigns fixed priority to the channel group.
1 = Assigns rotating priority to the channel group.
Reserved. Must be 0
DMA Channel Group Enable: Both channel groups are
enabled following part reset. Disabling channel group 4-7
also disables channel group 0-3, which is cascaded
through channel 4.
0 = Enables the DMA channel group
1 = Disables the DMA channel group
Reserved. Must be 0.
a. View 1 describes the control registers for Channels 0-3.
b. View 2 describes the control registers for Channels 4-7.
Bit Reset
Value
0h
Xh
0h
X
0h
Bit Access
WO
WO
Intel^® EP80579 Integrated Processor Product Line Datasheet
770
August 2009
Order Number: 320066-003US