EP80579 Datasheet, PDF (389/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.0 IMCH Registers
16.1
Warning:
IMCH Registers: Bus 0, Device 0, Function 0
The Integrated Memory Controller Hub (IMCH) registers are in Bus 0, Device 0,
Function 0. Table 16-1 provides the register address map for this device and function.
Address locations that are not listed are considered reserved register locations. Reads
to reserved registers may return non-zero values. Writes to reserved locations may
cause system failure.
Table 16-1. Bus 0, Device 0, Function 0: Summary of IMCH PCI Configuration Registers
(Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
00h
02h
04h
06h
08h
0Ah
0Bh
0Eh
14h
2Ch
2Eh
4Ch
50h
51h
53h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
01h
03h
05h
07h
08h
0Ah
0Bh
0Eh
17h
2Dh
2Fh
4Fh
50h
51h
53h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
“Offset 00h: VID – Vendor Identification Register” on page 391
“Offset 02h: DID – Device Identification Register” on page 391
“Offset 04h: PCICMD: PCI Command Register” on page 392
“Offset 06h: PCISTS: PCI Status Register” on page 393
“Offset 8h: RID - Revision Identification Register” on page 394
“Offset 0Ah: SUBC - Sub-Class Code Register” on page 394
“Offset 0Bh: BCC – Base Class Code Register” on page 394
“Offset 0Eh: HDR - Header Type Register” on page 395
“Offset 14h: SMRBASE - System Memory RCOMP Base Address Register” on
page 396
“Offset 2Ch: SVID - Subsystem Vendor Identification Register” on page 396
“Offset 2Eh: SID - Subsystem Identification Register” on page 397
“Offset 4Ch: NSIBAR - Root Complex Block Address Register” on page 397
“Offset 50h: CFG0- IMCH Configuration 0 Register” on page 398
“Offset 51h: IMCH_CFG1 – IMCH Configuration 1 Register” on page 399
“Offset 53h: CFGNS1 - Configuration 1 (Non-Sticky) Register” on page 399
“Offset 58h: FDHC - Fixed DRAM Hole Control Register” on page 400
“Offset 59h: PAM0 - Programmable Attribute Map 0 Register” on page 401
“Offset 5Ah: PAM1: Programmable Attribute Map 1 Register” on page 402
“Offset 5Bh: PAM2 - Programmable Attribute Map 2 Register” on page 403
“Offset 5Ch: PAM3 - Programmable Attribute Map 3 Register” on page 404
“Offset 5Dh: PAM4 - Programmable Attribute Map 4 Register” on page 405
“Offset 5Eh: PAM5 - Programmable Attribute Map 5 Register” on page 406
“Offset 5FH: PAM6 - Programmable Attribute Map 6 Register” on page 407
Default
Value
8086h
5020h
0006h
0010h
Variable
00h
06h
80h
00000000h
0000h
0000h
00000000h
0Ch
00000h
00h
00h
00h
00h
00h
00h
00h
00h
00h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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