EP80579 Datasheet, PDF (1008/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-40. Offset 20h: USB2CMD - USB 2.0 Command Register (Sheet 2 of 2)
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 20h
Offset End: 23h
Size: 32 bit
Default: 00080000h
Power Well: Core
Bit Range
04
03 :02
01
Bit Acronym
Bit Description
Sticky
P_SCEN
FLS
HCRESET
Periodic Schedule Enable: Default 0b. This bit controls
whether the host controller skips processing the Periodic
Schedule. Values mean:
0 = Do not process the Periodic Schedule
1 = Use the PERIODICLISTBASE register to access the
Periodic Schedule.
Frame List Size: Hardwired to 00b because it only
supports the 1024-element frame list size.
Host Controller Reset: This control bit used by software
to reset the host controller. The effects of this on Root Hub
registers are similar to a Chip Hardware Reset (i.e.,
RSMRST# assertion and PWROK deassertion).
When software writes a one to this bit, the Host Controller
resets its internal pipelines, timers, counters, state
machines, etc. to their initial value. Any transaction
currently in progress on USB is immediately terminated. A
USB reset is not driven on downstream ports.
PCI Configuration registers and Host Controller Capability
Registers are not affected by this reset.
All operational registers, including port registers and port
state machines are set to their initial values. Port
ownership reverts to the companion host controller(s),
with the side effects described in the EHCI Specification.
Software must reinitialize the host controller in order to
return the host controller to an operational state.
This bit is set to zero by the Host Controller when the
reset process is complete. Software cannot terminate the
reset process early by writing a zero to this register.
Software must not set this bit to a one when the HCHalted
bit in the USBSTS register is a zero. Attempting to reset
an actively running host controller will result in undefined
behavior.
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RO
RW
Run/Stop: Default 0b. 1=Run. 0=Stop.
1 = The Host Controller proceeds with execution of the
schedule. The Host Controller continues execution as
long as this bit is set to a 1.
0 = The Host Controller completes the current and any
actively pipelined transactions on the USB and then
halts. The Host Controller must halt within 16
microframes after software clears the Run bit. The HC
Halted bit in the status register indicates when the
Host Controller has finished its pending pipelined
transactions and has entered the stopped state.
Software must not write a 1 to this field unless the
host controller is in the Halted state (i.e., HCHalted in
00
RS
the USBSTS register is a one).
The following table explains how the different
combinations of Run and Halted must be interpreted:
Run/Stop Halted
Interpretation
0
0
Valid - in the process of halting
0
1
Valid - halted
1
0
Valid - running
1
1
clears immediately
Invalid - the HCHalted bit
Memory read cycles initiated by the EHC that receive any
status other than Successful will result in this bit being
cleared (and also affect the Host Error bit).
0h
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1008
August 2009
Order Number: 320066-003US