EP80579 Datasheet, PDF (1644/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1.5 Offset 0010h: TS_Test - Time Sync Test Register
Register
Name
TS_Test
Access
(See below.) Reset Value x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(Reserved)
rx_snap_cfg tx_snap_cfg
tenb tm
Table 41-15. Offset 0010h: TS_Test Register (Sheet 1 of 2)
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 00000010h
Offset End: 00000013h
Size: 32 bits
Default: 0000h
Power Well: Core
Bit Range
31 : 12
11 : 8
7: 4
Bit Acronym
Bit Description
Sticky
RSVD
Reserved for future use.
rx_snap_cfg
Determines which RX channel activity is reflected on
TS_RX_SNAP_TAKEN
0000 -- Channel 0 RX snapshot activity monitored
0001 -- Channel 1 RX snapshot activity monitored
0010 -- Channel 2 RX snapshot activity monitored
0011 -- Channel 3 RX snapshot activity monitored
0100 -- Channel 4 RX snapshot activity monitored
0101 -- RESERVED for Channel 5 RX snapshot activity
monitored
0110 -- RESERVED for Channel 6 RX snapshot activity
monitored
0111 -- RESERVED for Channel 7 RX snapshot activity
monitored
1000 -- CAN 0 snapshot activity monitored
1001 -- CAN 1 snapshot activity monitored
1010 -1111 -- RESERVED
Note: The ts_rx_snap_taken signal is non-zero
when the tm bit is set and will be a pulse that is
eight pclk cycles wide.
tx_snap_cfg
Determines which TX channel activity is reflected on
TS_TX_SNAP_TAKEN
0000 -- Channel 0 TX snapshot activity monitored
0001 -- Channel 1 TX snapshot activity monitored
0010 -- Channel 2 TX snapshot activity monitored
0011 -- Channel 3 TX snapshot activity monitored
0100 -- Channel 4 TX snapshot activity monitored
0101 -- RESERVED for Channel 5 TX snapshot activity
monitored
0110 -- RESERVED for Channel 6 TX snapshot activity
monitored
0111 -- RESERVED for Channel 7 TX snapshot activity
monitored
1000 -- CAN 0 snapshot activity monitored
1001 -- CAN 1 snapshot activity monitored
1010 -1111 -- RESERVED
Note: The ts_tx_snap_taken signal is non-zero
when the tm bit is set and will be a pulse that is
eight pclk cycles wide.
Bit Reset
Value
x
0000h
0000h
Bit Access
RV
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1644
August 2009
Order Number: 320066-003US