EP80579 Datasheet, PDF (886/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
If the HBA was transmitting a Data FIS it does not retry the FIS and waits for software
to clear the PxCMD.ST bit to '0'. The HBA shall retransmit a non-Data FIS continuously
after a failure until either the transfer succeeds or system software stops the controller
by clearing PxCMD.ST to '0'.
— Received Disparity Error / Illegal Character (K28.3): When a disparity error is
encountered, the HBA assumes the disparity of this character is correct and
resets the running disparity counter in the 8b/10b decoder. No error bits are
set.
— Received Disparity Error / Illegal Character (D): When this occurs, the HBA
returns R_ERR at the end of the FIS. It sets PxSERR.DIAG.B. Note that
PxIS.IFS/PxIS.INFS shall not be set; the CRC error that is likely to occur due to
this event will set the appropriate bit. If there is an illegal character outside the
FIS boundaries, the HBA may ignore the event and is not required to set
PxSERR.DIAG.B.
— PhyRdy Dropping Unexpectedly: When this occurs, the HBA returns to idle. If
the PhyRdy signal dropped during the middle of a command, the HBA may have
to be restarted. If the PhyRdy signal dropped outside of a FIS, neither the
PxIS.IFS nor the PxIS.INFS bits shall be set.
— Calculated Different CRC than Received: When this occurs, the HBA returns
R_ERR and returns to idle. It sets PxSERR.DIAG.C
— Incorrect FIS or FIS with Illegal Length for Corresponding FIS Type Received:
When this occurs, the HBA returns R_ERR at end of the FIS, shall not post the
FIS to memory, and returns to idle. It sets PxSERR.ERR.P. This can only be
done for supported FIS types. An unknown FIS is not considered an illegal FIS,
unless the length received is more than 64 bytes. If an unknown FIS arrives
with length <= 64 bytes, it is posted and the HBA continues normal operation.
— Internal Buffer Overflow: This occurs when the HBA sends a HOLD, but a
HOLDA was not received quickly enough by the HBA, and the HBA’s internal
data FIFOs overflow. The HBA returns R_ERR at the end of the FIS. It sets
PxSERR.ERR.P.
— HBA Receives R_ERR: If the HBA receives an R_ERR to a FIS it was
transmitting, it sets PxSERR.DIAG.H.
— FIS received from a device, where both BSY and DRQ are to be updated in the
Status register and both PxTFD.STS.BSY and PxTFD.STS.DRQ are cleared:
When this occurs, the HBA returns R_OK, does not set any error bits, and does
not update any registers or the received FIS area based on the received FIS
(i.e. the FIS is ignored).
— It is system software's responsibility to check the PxSERR register periodically
to determine if the interface is operating cleanly, and take appropriate actions
(such as going down to Generation1 speed if operating at a higher speed or
notifying the user) when interface errors occur.
23.6.2.1.3
Device Errors
When a FIS arrives that updates the taskfile, the HBA checks to see if PxTFD.STS.ERR
is set. If it is, and PxIE.TFEE is set, the HBA shall generate an interrupt and stop
processing any more commands.
23.6.2.1.4
Command List Overflow
Command list overflow is defined as software building a command table that has fewer
total bytes than the transaction given to the device. On device writes, the HBA will run
out of data, and on reads, there will be no room to put the data.
Intel^® EP80579 Integrated Processor Product Line Datasheet
886
August 2009
Order Number: 320066-003US