EP80579 Datasheet, PDF (304/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
11.4.8
11.4.8.1
11.4.8.2
Scrubbing Support
The memory controller will support both demand scrubbing and background scrubbing
in hardware. This section provide details of the scrubbing mechanism.
Demand Scrubbing
When the controller detects a single bit error on a DRAM read, the ECC logic fixes the
single bit error and returns the corrected data to the requester. The controller also
writes the corrected data back into DRAM using the demand scrub operation.
Background Scrubbing
The controller supports a simple state machine that periodically injects read
transactions into the stream. The scrub rate meets a general requirement for scrubbing
a 4GB memory capacity every 24 hours. It can also be programmed to scrub the entire
DDR at faster rates, if that is desired. Rates available extend from an entire scrub every
few days, to every day, every hour, every minute, and even very fast rates, mainly
used for validation purposes. Data for a background scrub read operation is discarded if
no error is detected on the read. When a single bit error is detected on a background
scrub read transaction, the mechanism specified in Figure 11.4.8.1 is used to correct
the single bit error in DRAM. The read data is dropped. When a double bit error is
detected on a background scrub read transaction, the controller log the error and
interrupts the IA-32 core.
11.5
Error Handling
The memory controller accesses may encounter data with ECC violations and/or parity
errors.
• For writes with bad parity, as indicated on bits in the command from either AIOC
memory target (MT) or IMCH, the memory controller will execute the write,
poisoning the data as it writes it to DDR. Please see Table 11-17 for the granularity
of poisoned data. Poisoning is accomplished by inverting each bit of ECC calculated
for that particular write, based on the bad write data sent to the memory controller
from AIOC or IMCH.
• For reads from DDR with single bit parity errors, the memory controller will correct
all correctable errors, and return the data, to either requestor, corrected, and
without a bad parity indication. Status logging, as discussed above, will be done.
• For reads from DDR with multiple bit, uncorrectable ECC violations, the memory
controller will return the data to either requestor, however, a bad parity indication
will be driven back with the data. Please see Table 11-17 for the granularity of
poisoned data. AIOC memory target (MT) or IMCH should poison the data when
seeing the bad parity bit set, along with the read data returned.
Intel^® EP80579 Integrated Processor Product Line Datasheet
304
August 2009
Order Number: 320066-003US