EP80579 Datasheet, PDF (838/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.1.4.3 Offset 84h: MA – Message Signaled Interrupt Message Address
Register
Table 23-30. Offset 84h: MA – Message Signaled Interrupt Message Address Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 84h
Offset End: 87h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 02
01 : 00
Bit Acronym
Bit Description
Sticky
ADDR
Reserved
Address (ADDR): Lower 32 bits of the system specified
message address, always DWORD aligned.
Reserved
Bit Reset
Value
0h
00h
Bit Access
RW
RO
23.1.4.4 Offset 88h: MD – Message Signaled Interrupt Message Data Register
Table 23-31. Offset 88h: MD – Message Signaled Interrupt Message Data Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 88h
Offset End: 89h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 00
Bit Acronym
Bit Description
Sticky
DATA
Data (DATA): This 16-bit field is programmed by system
software if MSI is enabled. Its content is driven onto the
lower word of the data bus of the MSI memory write
transaction.
Bit Reset
Value
0h
Bit Access
RW
23.1.5
Warning:
Note:
Additional Configuration Registers
The default values are defined with an h for hex, a bi for binary, or 00 for zero. If there
is not a letter following the default value, assume it is a binary number.
Address locations that are not listed are considered reserved register locations. Reads
to reserved registers may return non-zero values. Writes to reserved locations may
cause system failure.
Reserved bits are Read Only.
Start
90
92
A8
AC
End
90
92
AB
AF
Symbol
MAP
PCS
SATACR0
SATACR1
Name
Port Mapping Register
Port Control and Status
Serial ATA Capability Register 0
Serial ATA Capability Register 1
Intel^® EP80579 Integrated Processor Product Line Datasheet
838
August 2009
Order Number: 320066-003US