EP80579 Datasheet, PDF (51/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
50.2.2.2 Processor Passive Cooling ...............................................................1915
50.2.2.3 On-Demand Passive Cooling ............................................................1915
Figures
2-1
Intel^® EP80579 Integrated Processor Block Diagram ............................................. 104
2-2
Intel^® EP80579 Integrated Processor with Intel® QuickAssist
Technology Block Diagram................................................................................. 105
3-1
Device-Centric Logical View of EP80579 Devices ................................................... 112
3-2
Logical Overview of the CMI PCI Infrastructure..................................................... 115
3-3
Attaching the AIOC to the CMI PCI Fabric (Logical Perspective) .............................. 120
3-4
Overview of PCI infrastructure for On-die Devices................................................. 121
4-1
Logical Overview of Signaling Architecture ........................................................... 131
4-2
Logical View of Signaling Flow ............................................................................ 134
4-3
Signal Bridging ................................................................................................ 135
6-1
Powergood and Reset Interface .......................................................................... 164
6-2
Reset Sequence ............................................................................................... 167
6-3
EP80579 Rail Power On Sequence ...................................................................... 169
6-4
Power Rail Sequence Timings (Sustain Well Power Management) ............................ 170
6-5
Power Rail Sequence Timing (No Sustain Well Power Management)......................... 171
6-6
Powergood Reset Sequence ............................................................................... 172
6-7
Hard Reset Sequence........................................................................................ 173
6-8
BIOS Boot Flow (Cold Boot, S3/S4->S0) ............................................................. 175
6-9
Global System Power States and Transitions ........................................................ 177
9-1
CMI Block Diagram ........................................................................................... 255
10-1 Basic Memory Regions ...................................................................................... 267
10-2 DOS Legacy Region .......................................................................................... 269
10-3 Memory Region from 1 MByte through 4 GBytes ................................................... 271
10-4 PAM Associated Attribute Bits............................................................................. 273
11-1 Memory Address Tables for 64 Bit, Burst Size 4 and x8 DDR2 Devices ..................... 296
11-2 Memory Address Tables for 32 Bit, Burst Size 8 and x8 DDR2 Devices ..................... 296
11-3 2T and 1T Timing Mode..................................................................................... 297
11-4 ODT Timing on Back-to-Back Reads to Different Slots ........................................... 300
11-5 ODT Timing on Back-to-Back Writes to Different Slots ........................................... 301
12-1 Concept Diagram of EDMA Data Path .................................................................. 308
12-2 Conceptual Diagram of Four Channel EDMA Engine ............................................... 310
12-3 Chain Descriptor in Memory ............................................................................... 312
12-4 Chaining Mechanism ......................................................................................... 313
12-5 Source and Destination in Increment Mode Transfer.............................................. 319
12-6 Source in Decrement and Destination in Increment Mode Transfer (Byte Reversal).... 320
12-7 Source in Increment and Destination in 1-Byte Granularity Constant Mode Transfer .. 321
12-8 Source in Increment and Destination in 2-Byte Granularity Constant Mode Transfer .. 322
12-9 Source in Increment and Destination in 4-Byte Granularity Constant Mode Transfer .. 323
12-10 Source in Decrement and Destination in 1-Byte Granularity Constant Mode Transfer . 324
12-11 Source in Decrement and Destination in 2-Byte Granularity Constant Mode Transfer . 325
12-12 Source in Decrement and Destination in 4-Byte Granularity Constant Mode Transfer . 326
12-13 Source in Memory Initialization and Destination in Increment Mode Transfer ............ 327
12-14 Source in Buffer Initialization and Destination in 1-Byte Granularity Constant Mode
Transfer .......................................................................................................... 328
12-15 Source in Buffer Initialization and Destination in 2-Byte Granularity Constant Mode
Transfer .......................................................................................................... 328
12-16 Source in Buffer Initialization and Destination in 4-Byte Granularity Constant Mode
Transfer .......................................................................................................... 329
12-17 Initiation Flow Chart ......................................................................................... 343
12-18 Completion Flow Chart ...................................................................................... 344
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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