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EP80579 Datasheet, PDF (1215/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line | |||
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Intel® EP80579 Integrated Processor
34.0
34.1
34.2
PCI-to-PCI Bridge
Summary
The PCI-to-PCI bridge provides an interface between the AIOC and the MCH/IA. PCI-to-
PCI Bridge forwards data and commands from AIOC memory target to the PCI-to-PCI
bridge (Upstream interface). It also provide the IA a path into the AIOC via the PCI-to-
PCI bridge (Downstream Interface).
PCI-to-PCI Bridge Detailed Register Descriptions
Table 34-1. Bus 0, Device 4, Function 0: Summary of PCI-to-PCI Bridge PCI Configuration
Registers (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
0h
2h
4h
6h
8h
9h
Ch
Dh
Eh
10h
14h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
20h
22h
24h
26h
1h
3h
5h
7h
8h
Bh
Ch
Dh
Eh
14h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Fh
21h
23h
25h
27h
âOffset 0h: VID: Vendor Identification Registerâ on page 1217
âOffset 2h: DID: Device Identification Registerâ on page 1217
âOffset 4h: PCICMD: Device Command Registerâ on page 1217
âOffset 6h: PCISTS: PCI Device Status Registerâ on page 1218
âOffset 8h: RID: Revision ID Registerâ on page 1219
âOffset 9h: CC: Class Code Registerâ on page 1219
âOffset Ch: CLS: Cacheline Size Registerâ on page 1219
âOffset Dh: LT: Latency Timer Registerâ on page 1220
âOffset Eh: HDR: Header Type Registerâ on page 1220
âOffset 10h: CSRBAR0: Control and Status Registers Base Address Registerâ on
page 1220
âOffset 14h: CSRBAR1: Control and Status Registers Base Address Registerâ on
page 1221
âOffset 18h: PBNUM: Primary Bus Number Registerâ on page 1221
âOffset 19h: SECBNM: Secondary Bus Number Registerâ on page 1221
âOffset 1Ah: SUBBNM: Subordinate Bus Number Registerâ on page 1222
âOffset 1Bh: SECLT: Secondary Latency Timer Registerâ on page 1222
âOffset 1Ch: IOB: I/O Base Registerâ on page 1222
âOffset 1Dh: IOL: I/O Limit Registerâ on page 1223
âOffset 1Eh: SECSTA: Secondary Status Registerâ on page 1223
âOffset 20h: MEMB: Memory Base Registerâ on page 1224
âOffset 22h: MEML: Memory Limit Registerâ on page 1224
âOffset 24h: PMASE: Prefetchable Memory Base Registerâ on page 1225
âOffset 26h: PMLIMIT: Prefetchable Memory Limit Registerâ on page 1225
Default
Value
8086h
5037h
0h
10h
Variable
060400h
00h
00h
1h
00h
00h
00h
00h
00h
00h
F0
0
0h
FFF0
0
FFF1H
1H
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
1215
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