EP80579 Datasheet, PDF (1637/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.5.8
41.5.9
Interrupts
An level sensitive interrupt signal to the processor is generated when any of the
following conditions occur and are enabled:
• Auxiliary Master Mode snapshot is taken
• Auxiliary Slave Mode snapshot is taken
• Target time expiration.
• Auxiliary Target Time expiration
• Pulse per Second assertion
An interrupt enable mask must be set to allow any of the interrupts to pass to the core.
Reset
There are two types of reset:
• Power-on reset
• MMR write to soft reset register to initiate a channel
Each channel may be independently reset by SW by writing to the channel’s control
register.
If the GMII interface changes clock speeds (1000Mbps down to 100/10 Mbps), SW
must initiate a soft reset to the corresponding channel.
41.6
Register Summary
Writes to unused address space will have no affect. Reads to unused address space
may return indeterminate data. Neither situation should cause detrimental effects on
device operation unless specifically documented. Reserved bits within registers must be
written with their reset value unless otherwise stated.
For more information on the conventions the following register summaries adopt, see
Section 7.1, “Overview of Register Descriptions and Summaries” on page 183.
The IEEE 1588 Hardware Assist registers materialize in the PCI space
Table 41-10 summarizes the IEEE 1588 TSYNC materialization from the PCI
perspective.
Table 41-10. Bus M, Device 7, Function 0: Summary of IEEE 1588 TSYNC CSRs (Sheet 1 of
2)
Offset Start Offset End
Register ID - Description
00000000h
00000004h
00000008h
0000000Ch
00000010h
00000014h
00000003h
00000007h
0000000Bh
0000000Fh
00000013h
00000017h
“Offset 0000h: TS_Control Register” on page 1639
“Offset 0004h: TS_Event Register” on page 1641
“Offset 0008h: TS_Addend Register” on page 1643
“Offset 000Ch: TS_Accum Register” on page 1643
“Offset 0010h: TS_Test Register” on page 1644
“Offset 0014h: TS_PPS_Compare Register” on page 1646
Default
Value
00000000h
0022h
0000h
0000h
0000h
FFFFFFFFh
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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