EP80579 Datasheet, PDF (914/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.3.1.7 Offset 07h: HBD: Host Block Data Register
Table 24-25. Offset 07h: HBD: Host Block Data Register
Description:
View: PCI
BAR: SM_BASE (IO)
Bus:Device:Function: 0:31:3
Offset Start: 07h
Offset End: 07h
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
BDTA
Block Data: This is either a register, or a pointer into a
32-byte block array, depending upon whether the E32B
bit is set in the Auxiliary Control register. When the
E32B bit is cleared, this is a register containing a byte of
data to be sent on a block write or read from on a block
read.
When the E32B bit is set, reads and writes to this
register are used to access the 32-byte block data
storage array. An internal index pointer is used to
address the array, which is reset to 0 by reading the
HCTL register (offset 02h). The index pointer then
increments automatically upon each access to this
register. The transfer of block data into (read) or out of
(write) this storage array during an SMBus transaction
always starts at index address 0.
When the E2B bit is set, for writes, software will write
up to 32-bytes to this register as part of the setup for
the command. After the Host Controller has sent the
Address, Command, and Byte Count fields, it will send
the bytes in the SRAM pointed to by this register. When
the E2B bit is cleared for writes, software will place a
single byte in this register. After the host controller has
sent the address, command, and byte count fields, it
will send the byte in this register. If there is more data
to send, software will write the next series of bytes to
the SRAM pointed to by this register and clear the
DONE_STS bit. The controller will then send the next
byte. During the time between the last byte being
transmitted to the next byte being transmitted, the
controller will insert wait-states on the interface.
When the E2B bit is set for reads, after receiving the
byte count into the Data0 register, the first series of
data bytes go into the SRAM pointed to by this register.
If the byte count has been exhausted or the 32-byte
SRAM has been filled, the controller will generate an
SMI# or interrupt (depending on configuration) and set
the DONE_STS bit. Software will then read the data.
During the time between when the last byte is read
from the SRAM to when the DONE_STS bit is cleared,
the controller will insert wait-states on the interface.This
eight bit register is transmitted in the DATA1 field of the
SMB protocol during the execution of any command.
Bit Reset
Value
00h
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
914
August 2009
Order Number: 320066-003US