EP80579 Datasheet, PDF (1355/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Exact Unicast/Multicast - The destination address must exactly match one of 16
stored addresses. These addresses can be unicast or multicast.
Promiscuous Unicast - Receive all unicasts.
Multicast - The upper bits of the incoming packet's destination address index a bit
vector that indicates whether to accept the packet; if the bit in the vector is one,
accept the packet, otherwise, reject it. The EP80579’s GbE provides a 4096 bit
vector. Software provides four choices of which bits are used for indexing. These
are [47:36], [46:35], [45:34], or [43:32] of the internally stored representation of
the destination address.
Promiscuous multicast - Receive all multicast packets.
VLAN - Receive all VLAN packets that are for this station and have the appropriate
bit set in the VLAN filter table. A detailed discussion and explanation of VLAN
packet filtering is contained in “802.1q VLAN Packet Filtering” on page 1401.
Normally, only good packets are received. These are defined as those packets with no
CRC error, symbol error, sequence error, length error, alignment error, or where carrier
extension or RX_ERR errors are detected. However, if the store-bad-packet bit is set in
the Device Control register (RCTL.SBP), then bad packets that pass the filter function
are stored in host memory. Packet errors are indicated by error bits in the receive
descriptor (RDESC.ERRORS). It is possible to receive all packets, regardless of whether
they are bad, by setting the promiscuous enables and the store-bad-packet bit.
37.5.5.2
Receive Data Storage
Memory buffers pointed to by descriptors store packet data. Hardware supports various
receive buffer sizes; explicitly 256B, 512B, 1024B, 2048B, 4096B, 8192B, and 16384B.
Buffer size is selected by bit settings in the Receive Control register (RCTL.BSIZE &
RCTL.BSEX). See Section 37.6.4.1, “RCTL – Receive Control Register” for details.
The EP80579’s GbE places no alignment restrictions on receive memory buffer
addresses. This is desirable in situations where the receive buffer was allocated by
higher layers in the networking software stack, as these higher layers may have no
knowledge of a specific device's buffer alignment requirements.
Although alignment is completely unrestricted, it is highly recommended that software
allocate receive buffers on cache-line boundaries.
37.5.5.3 Receive Descriptor Format
A receive descriptor is a data structure that contains the receive data buffer address
and fields for hardware to store packet information. Refer to Figure 37-6, where the
shaded areas indicate fields that are modified by hardware upon packet reception.
Figure 37-6. Receive Descriptor (RDESC) Layout
63
48 47
40 39
32 31
16 15
0
0
Buffer Address[63:0]
8
Special
Errors
Status
Packet Checksum^†
Length
†
The checksum indicated here is the unadjusted “16 bit ones complement” of the packet. A software
assist may be required to back out appropriate information prior to sending it up to upper software
layers. The packet checksum is always reported in the first descriptor (even in the case of multi-
descriptor packets).
†
The Packet Checksum is reported in Little Endian format
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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