EP80579 Datasheet, PDF (1768/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
48.4.4.5 Synchronous Serial Port (SSP) Interface
Table 48-25. SSP Interface Signals
Signal Name
SSP_SCLK
SSP_SFRM
SSP_TXD
SSP_RXD
SSP_EXTCLK
IO Type
LVTTL,3.3V
LVTTL,3.3V
LVTTL,3.3V
LVTTL,3.3V
LVTTL,3.3V
TOTAL
Direction
Ball
Count
O
1
O
1
O
1
I
1
I
1
5
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
BSC
BSC
BSC
BSC
BSC
SSP Interface Clock: Serial bit-rate clock
(1.84MHz maximum frequency). This is the bit-
rate clock, driven from the SSP port to the
peripheral. Normally, it toggles only when data
is actively being transmitted.
SSP Interface Frame Indicator: This is the
framing signal and indicates the beginning and
the end of a serialized data word.
SSP Interface Transmit Data: This is the
transmit (i.e., outbound) serialized data lines.
The word length and MSB/LSB orientation are a
function of the selected serial data format.
SSP Interface Receive Data: This is the receive
(i.e., inbound) serialized data lines. The word
length and MSB/LSB orientation are a function
of the selected serial data format.
SSP Interface External Clock: This clock can be
selected to replace the internally-generated
clock that is used to generate the serial bit-rate
clock (SSPCLK).
48.4.4.6 IEEE 1588-2008 Hardware Assist Interface
Table 48-26. IEEE 1588-2008 Hardware Assist Interface Signals (Sheet 1 of 2)
Signal Name
1588_TESTMODE
_DATA
1588_PPS
ASMSSIG
AMMSSIG
IO Type
LVTTL,3.3V
LVTTL,3.3V
LVTTL,3.3V
LVTTL,3.3V
Direction
Ball
Count
O
1
O
1
I
1
I
1
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
BSC
BSC
BSC
BSC
IEEE 1588-2008 Hardware Assist Test Output:
This signal will reflect bits of the internal System
Timer depending on the setting of internal
control bits in the 1588_Test register.
IEEE 1588-2008 Hardware Assist Pulse Per
Second Output - This signal is asserted high
when a match occurs between the Compare
register and lower 32 bits of system time.
Clearing of this signal is under firmware control.
The register and pin can be used to create a
pulse per second event.
IEEE 1588-2008 Hardware Assist Auxiliary Slave
Mode Snapshot: An active high level on this
input causes a snapshot of system time to be
captured in the ASMS register.
IEEE 1588-2008 Hardware Assist Auxiliary
Master Mode Snapshot: An active high level on
this input causes a snapshot of system time to
be captured in the AMMS register.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1768
August 2009
Order Number: 320066-003US