EP80579 Datasheet, PDF (939/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
Host software must always clear the HOST_NOTIFY_STS bit after completing any
necessary reads of the address and data registers.
Table 24-59 shows the host notify protocol.
Table 24-59. Host Notify Protocol
Bit
1
2–8
9
10
Description
Start
SMB Host Addr - 7 bits
Write
ACK (or NACK)
Driven by:
External Master
External Master
External Master
CMI
11 – 17 Device Address - 7 bits
External Master
18 Unused- Hardwired to 0
19 ACK
20 – 27 Data Byte Low
28 ACK
29 – 36 Data Byte High
37 ACK
38 Stop
External Master
CMI
External Master
CMI
External Master
CMI
External Master
Comment:
Always 0001_000
Hardwired to 0
The CMI NACKs if HOST_NOTIFY_STS is 1
Indicates the address of the master; loaded in to the Notify
Device Address Register
7-bit-only address; this bit is inserted to complete the byte
Loaded in to the Notify Data Low Byte Register
Loaded in to the Notify Data High Byte Register
§§
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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