EP80579 Datasheet, PDF (401/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.17 Offset 59h: PAM0 - Programmable Attribute Map 0 Register
This register controls the read, write, and shadowing attributes of the BIOS area from
0F0000h-0FFFFFh. See Section 19.0.3, “PAM Memory Spaces” for more information on
PAM memory spaces.
Table 16-19. Offset 59h: PAM0 - Programmable Attribute Map 0 Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 59h
Offset End: 59h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 06
05 : 04
03 : 00
Bit Acronym
Bit Description
Sticky
Reserved
HIENABLE
Reserved
Reserved
Attribute Register: This field controls the steering of read
and write cycles that address the BIOS area from 0F0000
to 0FFFFF.
Encoding Description:
0 0 DRAM Disabled - All accesses are directed to NSI.
0 1 Read-Only - All reads are serviced by DRAM. All
writes are forwarded to NSI.
1 0 Write-Only - All writes are sent to DRAM. Reads are
serviced by NSI.
1 1 Normal DRAM Operation - All reads and writes are
serviced by DRAM.
Reserved
Bit Reset
Value
00b
00b
0h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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