EP80579 Datasheet, PDF (1140/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 30-28. APIC_RTE[0-39] - Redirection Table Entry (Sheet 2 of 3)
Description:
Offset: vector 0: 10h-11h, vector
Hex)) -(11h + (N*2 in Hex))
1:
12h-13h,
vector
23:
3Eh-3Fh,
vector
39:
5Eh-5Fh;
vector
N:
(10h+
(N*2
in
View: IA I
Win:Idx: APIC_WDW:APIC_IDX
Vector 0
10h at 02h
Offset Start: (4B)
Offset End: 11h at 02h
(4B)
Size: 64 bit^a
Default: XXXX00000001XXXXh
Power Well: Core
Bit Range
16
15
14
13
12
Bit Acronym
Bit Description
Sticky
MSK
TM
RIRR
POL
DS
Mask:
0 = Not masked; an edge or level on this interrupt pin
results in the delivery of the interrupt to the
destination.
1 = Masked; interrupts are not delivered nor held
pending. Setting this bit after the interrupt is
accepted by a local APIC has no effect on that
interrupt. This behavior is identical to the device
withdrawing the interrupt before it is posted to the
processor. It is software's responsibility to deal
with the case where the mask bit is set after the
interrupt message has been accepted by a local
APIC unit but before the interrupt is dispensed to
the processor.
Trigger Mode: This field indicates the type of signal on
the interrupt pin that triggers an interrupt.
0 = Edge triggered
1 = Level triggered
Remote IRR: This bit is used for level triggered
interrupts; its meaning is undefined for edge triggered
interrupts.
0 = Reset when an EOI message matches the VCT
field.
1 = Set when IOxAPIC sends the level interrupt
message to the processor.
Polarity: This bit specifies the polarity of each
interrupt input.
0 = Active high
1 = Active low
Delivery Status: This field contains the current status
of the delivery of this interrupt. Writes to this bit have
no effect.
0 = Idle. No activity for this interrupt.
1 = Pending. Interrupt has been injected but delivery
is not complete.
For edge triggered interrupts, this bit indicates
that an event has occurred but an interrupt
message has yet to be delivered to its targeted
destination. Once the interrupt message is
delivered, this bit will be cleared.
For level triggered interrupts, this bit is set
when the input event has occurred. This bit is
cleared when the interrupt input event is removed.
Note that as long as the interrupt input event is
active, this bit remains active regardless of
whether this interrupt has been delivered or not.
Bit Reset
Value
1
X
X
X
X
Bit Access
RW
RW
RW
RW
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1140
August 2009
Order Number: 320066-003US