EP80579 Datasheet, PDF (906/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.3.1
SMBus Controller I/O-Mapped Configuration Register
Descriptions
The SMBus Controller I/O-mapped configuration registers are mapped into I/O space
using register SM_BASE (see Section 24.2.1.9, “Offset 20h: SM_BASE: SMB Base
Address Register” on page 901).
24.3.1.1
Offset 00h: HSTS: Host Status Register
All status bits are set by hardware and cleared by the software writing a one to the
particular bit position. Writing a zero to any bit position has no effect.
Table 24-19. Offset 00h: HSTS: Host Status Register (Sheet 1 of 2)
Description:
View: PCI
BAR: SM_BASE (IO)
Bus:Device:Function: 0:31:3
Offset Start: 00h
Offset End: 00h
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
07
06
05
Bit Acronym
Bit Description
Sticky
BDS
IUS
SMBALERT_
STS
BYTE_DONE_STS:
0 = Software can clear this by writing a 1
1 = Host controller received a byte (for Block Read
commands) or if it has completed transmission of a
byte (for Block Write commands) when the 32-byte
buffer is not being used. This bit is set, even on the
last byte of the transfer. This bit is not set when
transmission is due to the LAN interface heartbeat.
This bit has no meaning for block transfers when the 32-
byte buffer is enabled.
When the last byte of a block message is received, the
host controller sets this bit. However, it does not
immediately set the INTR bit (bit 1 in this register).
When the interrupt handler clears the BYTE_DONE_STS
bit, the message is considered complete, and the host
controller will then set the INTR bit (and generate
another interrupt). Thus, for a block message of n
bytes, n+1 interrupts will be generated. The interrupt
handler needs to be implemented to handle these cases.
In Use Status:
0 = After a full PCI reset, a read to this bit returns a 0.
1 = After the first read, subsequent reads return a 1. A
write of a 1 to this bit resets the next read value to
0. Writing a 0 to this bit has no effect. Software can
poll this bit until it reads a 0, and then own the
usage of the host controller.
This bit has no other effect on the hardware, and is only
used as semaphore among various independent
software threads that may need to use the SMBus logic.
System Bus Alert Status:
0 = Interrupt or SMI# was not generated by
SMBALERT#. Software clears this bit by writing a 1
to it.
1 = The source of the interrupt or SMI# was the
SMBALERT# signal. This bit is only cleared by
software writing a 1 to the bit position or by CF9
RESET or RSMRST# going low (but not PLTRST#).
If the signal is programmed as a GPI, then this bit is
never set.
Bit Reset
Value
0h
0h
0h
Bit Access
RWC
RW
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
906
August 2009
Order Number: 320066-003US