EP80579 Datasheet, PDF (1378/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
• TXDCTL.WTHRESH = 0 and a descriptor which has RS set is ready to be written
back,
• Transmit Interrupt Delay timer expires, or
• TXDCTL.WTHRESH > 0 and TXDCTL.WTHRESH descriptors have accumulated.
For the first condition, write-backs are immediate. This is the default operation and is
backward compatible with the 82542 implementation. For this case, the Transmit
Interrupt delay function works as described in “Delayed Transmit Interrupts” on
page 1378.
The other two conditions are only valid if descriptor bursting is enabled “TXDCTL –
Transmit Descriptor Control Register” on page 1500. In the second condition, the “TIDV
– Transmit Interrupt Delay Value Register” on page 1499 is used to force timely write-
back of descriptors. The first packet after timer initialization starts the timer. Timer
expiration flushes any accumulated descriptors and sets an interrupt event
(ICR.TXDW).
For the final condition, if TXDCTL.WTHRESH descriptors are ready for write-back, the
write-back is performed.
37.5.6.9
Transmit Interrupts
Hardware supplies three transmit interrupts. These interrupts are initiated via the
following conditions:
Transmit Descriptor Ring empty (ICR.TXQE) - All descriptors have been
processed. The head pointer is equal to the tail pointer.
Descriptor done (Transmit Descriptor Write-back (ICR.TXDW)) - Set when
hardware writes back a descriptor with RS set. This is only expected to be used in
cases where, for example, the streams interface has run out of descriptors and
wants to be interrupted whenever progress is made.
Transmit Delayed Interrupt (ICR.TXDW) - In conjunction with IDE (Interrupt
Delay Enable), the ICR.TXDW indication is delayed per the TIDV and/or TADV
registers. The interrupt is set when one of the transmit interrupt countdown timers
expires. A Transmit Delayed Interrupt is scheduled for a transmit descriptor with its
RS and IDE bits both set. When a Transmit Delayed Interrupt occurs, the ICR.TXDW
interrupt cause bit is set (just as when a Transmit Descriptor Write-back interrupt
occurs). This interrupt may be masked in the same manner as the ICR.TXDW
interrupt. This interrupt will be used frequently by software that performs dynamic
transmit chaining, by adding packets one at a time to the transmit chain.
Note:
The transmit delay interrupt is indicated with the same interrupt bit as the transmit
write-back interrupt, ICR.TXDW. The transmit delay interrupt is only delayed in time as
discussed above.
Transmit Descriptor Ring Low Threshold Hit (ICR.TXD_LOW) - Set when the
total number of transmit descriptors available (as measured by the difference
between the TX descriptor ring Head and Tail pointer) hits the low threshold
specified in the TXDCTL.LWTHRESH field in the transmit descriptor control register.
37.5.6.9.1
Delayed Transmit Interrupts
This mechanism allows software the flexibility of delaying transmit interrupts until no
more descriptors are added to a transmit chain for a certain amount of time, rather
than when the device's head pointer catches the tail pointer. This will occur if the device
is processing packets slightly faster than the software, a likely scenario for gigabit
operations.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1378
August 2009
Order Number: 320066-003US