EP80579 Datasheet, PDF (663/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.6.1.12 Offset 2Ch: DCR0 - Channel 0 Descriptor Control Register
The Descriptor Control Register (DCR) contains control values for the DMA transfer on a
per descriptor basis. This register is loaded when the descriptor control field of the
chain descriptor is read from memory. The value for this register may vary from chain
descriptor to chain descriptor.
Table 16-308.Offset 2Ch: DCR0 - Channel 0 Descriptor Control Register (Sheet 1 of 2)
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 2Ch
Offset End: 2Fh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 29
28 : 19
18 : 17
16
15 : 14
13 : 12
11 : 09
08
07
Bit Acronym
Bit Description
Sticky
TC
Reserved
Granularity
Reserved
DADDM
SADDM
Reserved
SRCC
DSTC
PCI Express A-segment Traffic Class:
This field is used to set the Traffic Class field on the PCI
Express bus for transactions. This field has no effect on
memory to memory transactions.
Reserved
Destination Granularity:
00 1 byte granularity
01 2 byte granularity (DAR[0] and TCR[0] ignored)
10 4 byte granularity (DAR[1:0] and TCR[1:0]
ignored)
11 Reserved
These bits are loaded by the descriptor fetch only. This
field is ignored unless bits 15:14 are 01b (selecting
Constant Destination Mode).
When this field is enabled, the Destination Address and
Transfer Count Register must contain an integer
multiple of the granularity.
Reserved
Destination Processing Mode:
00 Increment mode
01 Constant mode (bits 18:17 set the granularity)
10 Reserved
11 Reserved
These bits are loaded by the descriptor fetch only.
Source Processing Mode:
00 Increment mode
01 Decrement mode
10 Buffer Initialization
11 Reserved
These bits are loaded by the descriptor fetch only.
Reserved
Source Coherency:
0 = Source is a non-coherent address space
1 = Source is a coherent address space
Destination Coherency:
0 = Destination is a non-coherent address space
1 = Destination is a coherent address space
For PCI-E writes (I/O), this bit inversely reflects the
state of the Snoop Not Required Attribute header bit:
0 = Snoop not required attribute bit = 1
1 = Snoop not required attribute bit = 0
Bit Reset
Value
000b
000h
00b
0b
00b
00b
000b
0b
0b
Bit Access
RO
RO
RO
RO
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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