EP80579 Datasheet, PDF (1136/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.3.3.2
APIC_DAT – Data Register
This register specifies the data to be read or written to the register pointed to by the
Index register. This register can be accessed only in Dword quantities. The register is
described in Section 30.3.4.
Table 30-22. APIC_DAT – Data Register
Description:
View: IA F
Base Address: FEC00000h
Offset Start: 0010h (4B)
Offset End: 0010h (4B)
Size: 32 bit
Default: 00h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
WDW
This is a register for the data to be read or written to the
APIC indirect register pointed to by the Index register
(Table 30-21).
Bit Reset
Value
00h
Bit Access
RW
30.3.3.3
APIC_EOI - EOI Register
When a write is issued to this register, the IOxAPIC checks the lower 8 bits written to
this register, and compares it with the vector field for each entry in the I/O Redirection
Table. When a match is found, RTE.RIRR for that entry is cleared. If multiple entries
have the same vector, each of those entries has RTE.RIRR cleared. Only bits 07:00 are
used and bits 31:08 are ignored.
Table 30-23. APIC_EOI - EOI Register
Description:
View: IA F
Base Address: FEC00000h
Offset Start: 0040h (4B)
Offset End: 0040h (4B)
Size: 32 bit
Default: 00h
Power Well: Core
Bit Range
31 : 08
07 : 00
Bit Acronym
Bit Description
Sticky
Reserved
REC
Reserved. software must always write a value of 0 to
these bits.
Redirection Entry Clear: When a write is issued to this
register, the
I/O APIC checks this field, and compares it with the
vector field for each entry in the I/O Redirection Table.
When a match is found, the Remote_IRR bit for that I/O
Redirection Entry is cleared.
Bit Reset
Value
00h
00h
Bit Access
WO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1136
August 2009
Order Number: 320066-003US