EP80579 Datasheet, PDF (1057/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 27-11. Offset 00h: PM1_STS – Power Management 1 Status Register (Sheet 2 of 2)
Description:
View: PCI
Size: 16 bit
BAR: PMBASE (IO)
Default: 0000h
Bus:Device:Function: 0:31:0
Offset Start: 00h
Offset End: 00h
Power Well: Core^a
Bit Range Bit Acronym
Bit Description
Sticky
08
07 : 06
05
04 01
00
PWRBTN_STS
This bit is set when the PWRBTN# signal is asserted
(low), independent of any other enable bit. See
PWRBTN_EN for the effect when PWRBTN_STS goes
active. PWRBTN_STS is always a wake event. This bit is
only set by hardware and can be cleared by software
writing a one to this bit position. This bit is not affected
by hard resets caused by a CF9 write, but is reset by
RSMRST#.
If the PWRBTN# signal is held low for more than 4
seconds, CMI clears the PWRBTN_STS bit, sets the
PWRBTNOR_STS bit, the system transitions to the S5
state, and only PWRBTN# is enabled as a wake event.
If PWRBTN_STS bit is cleared by software while the
PWRBTN# pin is still held low, this will not cause the
PWRBTN_STS bit to be set. The PWRBTN# signal must
go inactive and active again to set the PWRBTN_STS bit.
Note: The SMBus Unconditional Power down
message, the CPU Thermal Trip and the
Internal Thermal Sensors' Catastrophic
Condition result in behavior matching the
Powerbutton Override, which includes clearing
this bit.
Reserved Reserved
GBL_STS
0 = The SCI handler must then clear this bit by writing
a 1 to the bit location.
1 = Set when an SCI is generated due to BIOS wanting
the attention of the SCI handler. BIOS has a
corresponding bit, BIOS_RLS, which will cause an
SCI and set this bit.
This bit will not cause wake events or SMI#. This bit is
not effected by SCI_EN.
Note: GBL_STS being set will cause an SCI, even if
the SCI_EN bit is not set. Software must take
great care not to set the BIOS_RLS bit (which
causes GBL_STS to be set) if the SCI handler is
not in place.
Reserved Reserved
TMROF_STS
0 = The SCI or SMI# handler clears this bit by writing a
1 to the bit location.
1 = This bit gets set any time bit 22 of the 24-bit timer
goes low (bits are numbered from 0 to 23). This
will occur every 2.3435 seconds. Hence, it is highly
likely that a read to this register after reset will
yield a 1 in this field. When the TMROF_EN bit
(PMBASE + 02h, bit 0) is set, then the setting of
the TMROF_STS bit will additionally generate an
SCI or SMI# (depending on the SCI_EN).
a. Bits 0-7: Core, Bits 8-15: Resume (except 11 in RTC)
Bit Reset
Value
0h
0h
0h
000h
0h
Bit Access
RWC
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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