EP80579 Datasheet, PDF (1612/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
40.4.2.5
40.4.2.6
Serial Clock Polarity (SPO)
The serial clock (SSP_SCLK) polarity bit (SPO) selects the polarity of the inactive state
of the SSP_SCLK pin when Motorola SPI format is selected (FRF=00). For SPO=0, the
SSP_SCLK is held low in the inactive or idle state when the SSP is not transmitting/
receiving data. For SPO=1, the SSP_SCLK is held high during the inactive/idle state.
The programmed setting of the SPO alone does not determine which SSP_SCLK edge
is used to transmit or receive data. The SPO setting in combination with the SSP_SCLK
phase bit (SPH) determines this. Note that the SPO is ignored for all data frame
formats except for the Motorola SPI format (FRF=00).
Serial Clock Phase (SPH)
The serial clock (SSP_SCLK) phase bit (SPH) determines the phase relationship
between the SSP_SCLK and the serial frame (SSP_SFRM) pins when the Motorola SPI
format is selected (FRF=00). When SPH=0, SSP_SCLK remains in its inactive/idle
state (as determined by the SPO setting) for one full cycle after SSP_SFRM is asserted
low at the beginning of a frame. SSP_SCLK continues to transition for the rest of the
frame and is then held in its inactive state for one-half of an SSP_SCLK period before
SSP_SFRM is de-asserted high at the end of the frame. When SPH=1, SSP_SCLK
remains in its inactive/idle state (as determined by the SPO setting) for one-half cycle
after SSP_SFRM is asserted low at the beginning of a frame. SSP_SCLK continues to
transition for the rest of the frame and is then held in its inactive state for one full
SSP_SCLK period before SSP_SFRM is de-asserted high at the end of the frame. The
combination of the SPO and SPH settings determines when SSP_SCLK is active during
the assertion of SSP_SFRM and which SSP_SCLK edge is used to transmit and receive
data on the SSP_TXD and SSP_RXD pins. When SPO and SPH are programmed to the
same value (both 0 or both 1), transmit data is driven on the falling edge of SSP_SCLK
and receive data is latched on the rising edge of SSP_SCLK. When SPO and SPH are
programmed to opposite values (one 0 and the other 1), transmit date is driven on the
rising edge of SSP_SCLK and receive data is latched on the falling edge of SSP_SCLK.
Note that the SPH is ignored for all data frame formats except for the Motorola SPI
format (FRF=00).
Table 40-4 shows the pin timing for all four programming combinations of SPO and
SPH. Note that SPO inverts the polarity of the SSP_SCLK signal and SPH determines
the phase relationship between SSP_SCLK and SSP_SFRM, shifting the SSP_SCLK
signal one-half phase to the left or right during the assertion of SSP_SFRM.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1612
August 2009
Order Number: 320066-003US