EP80579 Datasheet, PDF (615/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
RCVEN_OUT Lookup Table
DDRIOMC2
[MASTCNTL]
7
6
5
4
3
2
1
0
DRRTC RCVEN [2:0]
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
5
4
3
2
1
0
5
4
4
3
2
1
1
0
4
4
3
3
2
1
1
0
3
3
2
2
1
1
0
0
2
2
2
1
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
For example, if the DDRIOMC2.MASTCNTL is set to 0x7, the receiver enable delay can
be varied over eight cycle in 256 steps, one step for each DRRTC RCVEN setting. If
DDRIOMC2.MASTCNTL is set to 0x3, however, the number of steps is reduced to 128,
such that half of the DRRTC RCVEN settings do not produce an increase in delay from
the previous setting.
16.5.1.11 Offset A4h: DRRTC00 - Receive Enable Reference Output Timing
Control Register
This register determines DQS 3, 2, 1, & 0 input buffer enable timing delay
Table 16-237.Offset A4h: DRRTC00 - Receive Enable Reference Output Timing Control
Register
Description: DRRTC00: Receive Enable Reference Output Timing Control Register
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: A4h
Offset End: A7h
Size: 32 bit
Default: 06060606h
Power Well: Core
Bit Range
31 :24
23 :16
15 :08
7 :00
Bit Acronym
Bit Description
RCVEN03
RCVEN02
RCVEN01
RCVEN00
Receiver enable delay for DQS3
Receiver enable delay for DQS2
Receiver enable delay for DQS1
Receiver enable delay for DQS0
Sticky
Y
Y
Y
Y
Bit Reset
Value
06h
06h
06h
06h
Bit Access
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
615