EP80579 Datasheet, PDF (314/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
12.3.4
12.3.5
Note:
Scatter/Gather Transfer
The EDMA descriptors in memory may be defined such that they cause the channel to
perform typical scatter/gather data transfers. To “gather” data, software may create a
linked list of descriptors that will move non-contiguous source blocks of data into a
contiguous set of destination blocks. To “scatter” data, software may create a linked list
of descriptors that will move contiguous blocks of source data to non-contiguous
destination blocks. It is even possible to program the EDMA transfer descriptors in such
a way that some blocks of source data within a single chain are moved to new memory
locations, while other blocks are moved out to the I/O subsystem.
There is no hardware restriction limiting the nature of source and destination address
ranges, other than that the source and destination types (memory or I/O subsystem)
must match the descriptor address mappings. The IMCH aborts the EDMA operation
and reports a programming error if this requirement is not met.
Appending to a Descriptor Chain
After an EDMA channel has started processing a linked list of descriptors, the
application software may need to append a chain descriptor to the end of the current
chain without tearing down the transfer in progress. Such an operation requires a
mechanism to guarantee that a descriptor is never in the process of modification by the
IA-32 core while being retrieved by the EDMA channel (This would result in a hybrid
descriptor loaded into the corresponding EDMA channel register set, and spurious
operation). The suspend function of the EDMA controller is defined to facilitate this type
of usage.
The preferred mechanism for appending to a linked list currently being processed is to
suspend the current transfer, modify the terminal chain descriptor to update its Next
Descriptor Address field(s), and then allow the transfer to resume. This is accomplished
by first setting the Suspend bit in the Channel Control Register (CCR) followed by a
read of the Channel Status Register (CSR) to verify that the suspend has taken
effect.The Next Descriptor Address fields of the terminal chain descriptor in the current
linked list are updated with the address of the first descriptor to be appended. After this
update has occurred, software then clears the Suspend bit, sets the Channel Resume
bit and allows execution to proceed.
A single write to the CCR may update both bits simultaneously.
This append algorithm covers the following cases:
• The EDMA channel has completed execution of the terminal descriptor in the
original chain, and is idle. The EDMA channel examines the Channel Resume bit
when the Channel Control Register (CCR) is written. If the bit is set, the EDMA
channel will automatically clear the bit and re-read the last chain descriptor (as
indicated by CDAR/CDUAR), which updates NDAR with the appended chain
descriptor address. A non-null value in NDAR will result in a fetch of the target
chain descriptor, and resumed execution. (If the resulting NDAR/NDUAR pair
remains null, the EDMA channel will remain idle.)
• The EDMA channel is executing a descriptor prior to the terminal chain descriptor in
the linked list. Regardless of whether the channel completes execution of its
current descriptor prior to the CCR write to clear Suspend and set Channel Resume,
the channel will re-read the current chain descriptor in response to the Channel
Resume bit. The next chain descriptor in the chain will be fetched from the address
indicated by NDAR/NDUAR, and the channel will continue execution. The appended
chain descriptor (or descriptors) will be executed after the channel reaches the end
of the original chain.
• The channel is executing the terminal chain descriptor at the time of the suspend
command. The channel will complete the final chain descriptor of the original linked
Intel^® EP80579 Integrated Processor Product Line Datasheet
314
August 2009
Order Number: 320066-003US