EP80579 Datasheet, PDF (1834/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
49.5.1.2.1 Power Management Timing Diagrams
Figure 49-1. G3 (Mechanical Off) to S0 Timings
System
State
STPCLK#,
CPUSLP#
Processor I/F
signals
PLTRST#,
PCIRST#
SUS_STAT#
PWROK,
VRMPWRGD
Vcc
Supplies
SLP_S3#
SLP_S4#
SLP_S5#
G3
G3 S5 S4
S3
S0
t215
Strap Values
t218
t217
t214
t230
t233
t234
t232
SUSCLK
RSMRST#
VCCSus
t231
t204
Running
Figure 49-2. S0 to S1 to S0 Timing
S0 state
B6550-01
STATE
S0
STPCLK#
NSI
Message
CPUSLP#
Wake Event
S0 S1
t280
t281
S1
S1 S0
S0
t301
t271
B6552-01
Intel^® EP80579 Integrated Processor Product Line Datasheet
1834
August 2009
Order Number: 320066-003US