EP80579 Datasheet, PDF (990/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.2.1.19 Offset 54h: PM_CS - Power Management Control/Status Register
Table 26-21. Offset 54h: PM_CS - Power Management Control/Status Register
Description:
Reset
Reset
(bits
(bits
15:08):Suspend
1:0):Core Well.
Well,
not
D3-to-D0
nor
core
well
reset.
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 54h
Offset End: 55h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15
14 :13
12 :09
08
07 :02
01 :00
Bit Acronym
Bit Description
Sticky
PME_Status
Data_Scale
Data_Select
PME_En
Reserved
PowerState
0 = Writing a 0 has no effect.
1 = Set when EHC would normally assert the PME# signal
independent of the state of the PME_En bit.
Note: Writing a 1 to this bit will clear it and cause the internal
PME to deassert (if enabled). This bit must be explicitly
cleared by the operating system each time the operating
system is loaded.
Hardwired to “00” because it does not support the associated Data
register.
Hardwired to “0000” because it does not support the associated
Data register.
A ‘1’ enables EHC to generate an internal PME signal when
PME_Status is ‘1’. This bit must be explicitly cleared by the
operating system each time it is initially loaded.
Reserved
This 2-bit field is used both to determine the current power state of
EHC function and to set a new power state. The definition of the
field values are:
00b – D0 state
11b – D3_HOT state
If software attempts to write a value of 10b or 01b in to this field,
the write operation must complete normally; however, the data is
discarded and no state change occurs.
When in the D3hot state, accesses to the EHC memory range must
not be accessible, but the configuration space must still be
accessible.
When not in the D0 state, the generation of the interrupt output is
blocked. Specifically, the PIRQ[A] is not asserted by CMI when not
in the D0 state.
When software changes this value from the D3_HOT state to the D0
state, an internal warm (soft) reset is generated, and software
must reinitialize the function.
Bit Reset
Value
0h
00h
0000h
0h
0h
00h
Bit Access
RWC
RO
RO
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
990
August 2009
Order Number: 320066-003US