EP80579 Datasheet, PDF (1100/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
28.1.1.3 Offset 92h: PORT92 - Fast A20 and Init Register
Table 28-5. Offset 92h: PORT92 - Fast A20 and Init Register
Description:
View: IA F
Base Address: 0000h (IO)
Offset Start: 92h
Offset End: 92h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 02
01
Bit Acronym
Bit Description
Sticky
Reserved
ALT_A20_
GATE
Reserved.
Alternate A20 Gate:
0 = The A20M# signal can potentially go active. This bit is
ORed with the A20GATE input signal to generate
A20M# to the processor.
1 = A20M# signal disabled.
Bit Reset
Value
00h
0b
Bit Access
RW
INIT# forced active:
00
INIT_NOW
0 = INIT# is not forced to be active
1 = When this bit transitions from a 0 to a 1, it forces
INIT# active for 16 PCI clocks.
0b
RW
28.1.1.4 Offset F0h: COPROC_ERR - Coprocessor Error Register
Table 28-6. Offset F0h: COPROC_ERR - Coprocessor Error Register
Description:
View: IA F
Base Address: 0000h (IO)
Offset Start: F0h
Offset End: F0h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
OPROC_
ERR
Any value written to this register causes IGNNE# to go
active, if FERR# generates an internal IRQ13. In order for
FERR# to generate an internal IRQ13, the Coprocessor
Error Enable bit (Section 17.1.5.5, “Offset 31FFh: OIC -
Other Interrupt Control Register”, bit 1) must be set to 1.
Bit Reset
Value
00h
Bit Access
WO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1100
August 2009
Order Number: 320066-003US