EP80579 Datasheet, PDF (1488/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.4.14 MTA[0-127] – 128 Multicast Table Array Registers
There is one register per 32 bits of the Multicast Address Table for a total of 128
registers (thus the MTA[127:0] designation). The size of the word array depends on the
number of bits implemented in the multicast address table. Software must mask to the
desired bit on reads and supply a 32-bit word on writes. Refer to “Receive Initialization”
on page 1348 for details on initialization and usage.
Table 37-63. MTA[0-127] – 128 Multicast Table Array Registers
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 5200h at 4h
Offset End: 5203h at 4h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 5200h at 4h
Offset End: 5203h at 4h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 5200h at 4h
Offset End: 5203h at 4h
Size: 32 bits
Default: XXXX_XXXXh
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
Vector
32b vector of multicast address filter table information.
Sticky
Bit Reset
Value
X
Bit Access
RW
37.6.4.15 RAL[0-15] – Receive Address Low Register
These registers contain the lower bits of the 48 bit Ethernet address.
Table 37-64. RAL[0-15] - Receive Address Low Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 5400h at 8h
Offset End: 5403h at 8h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 5400h at 8h
Offset End: 5403h at 8h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 5400h at 8h
Offset End: 5403h at 8h
Size: 32 bits
Default: XXXXXXXXh
Power
Well:
GbE0: Aux
2: Core
Gbe1/
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
RAL
Receive Address Low. The lower 32 bits of the 48 bit
Ethernet address.
Bit Reset
Value
X
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1488
August 2009
Order Number: 320066-003US