EP80579 Datasheet, PDF (1665/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1.25 Offset 0140h: TS_CANx_Status[0-1] - Time Synchronization Channel
Event Register (Per CAN Channel)
Register
Name
TS_CANx_Status
Access
(See below.) Reset Value x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
*Address offsets per channel…
CAN 0 = 0x140
CAN 1 = 0x150
Table 41-35. Offset 0140h: TS_CANx_Status[0-1] - Time Synchronization Channel Event
Register (Per CAN Channel)
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
0140h at
Offset Start: 10h
Offset End: 0143h at
10h
Size: 32 bits
Default: 0000h
Power Well: Core
Bit Range
31 : 02
1: 1
0: 0
Bit Acronym
Bit Description
Sticky
Reserved
valid
ovr
Reserved for future use.
Snapshot Valid. This bit is automatically set when a CAN
interrupt has caused a snapshot to be taken. It indicates
that the current system time value has been captured in
the CAN_Snapshot register t.
This bit remains set until the firmware writes a '1' to this
bit location.
Snapshot Overrun. If a second snapshot is taken while
the valid flag is still set, then the overrun error bit (ovr) in
this register is set to a '1'. This indication notifies the
firmware that a previous snapshot was overwritten by the
current snapshot and never read.
To clear this bit, write a ‘1’ to it.
Bit Reset
Value
0h
0h
0h
Bit Access
RV
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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