EP80579 Datasheet, PDF (1597/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
39.6.1.10 Offset 0000002Ch: TxMessageDataLow[0-7] - Transmit Message Data
Low
Note:
These registers are implemented in the SRAM which does not have the capability to
mask writes to reserved bits. Therefore, reserved bits in this CSR will be RW. Software
should treat these bits as reserved and not change the reset value of these bits.
Note:
These registers are implemented in SRAM which is not initialized at power-up or upon
reset. So before enabling the CAN, software needs to update these CSR’s with the reset
values.
Table 39-15. Offset 0000002Ch: TxMessageDataLow[0-7] - Transmit Message Data Low
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:4:0
0000002Ch
Offset Start: at 10h
Offset End: 0000002Fh
at 10h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:5:0
0000002Ch
Offset Start: at 10h
Offset End: 0000002Fh
at 10h
Size: 32 bit
Default: XXXXXXXXh
Power Well: Core
Bit Range
31 :00
Bit Acronym
Bit Description
DataLow TxMessage0 Buffer. Data [31:0].
Sticky
Bit Reset
Value
Xh
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1597