EP80579 Datasheet, PDF (729/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
Warning:
Note:
Warning:
7. If step 5 (power button press) is unsuccessful in waking the system, the CMI
continues sending a message every period. The CMI does not attempt to
automatically reboot again. The CMI starts sending a message every period (30-32
seconds). This continues until some external intervention occurs (reset, power
failure, etc.).
A system that has locked up and can not be restarted with the power button press is
assumed to have broken hardware (bad power supply, short circuit on some bus, etc.),
and is beyond the CMI’s recovery mechanisms.
8. After step 3 (unsuccessful reboot after third timeout), if a reset is attempted (using
a button that pulses PWROK low or via the message on the SMBus Slave Interface),
the CMI attempts to reset the system.
9. After step 8 (reset attempt) if the reset is successful, then the BIOS is run. The CMI
continues sending a message every period until the BIOS clears the
SECOND_TO_STS bit.
It is important the BIOS clears the SECOND_TO_STS bit, as the messages interfere
with the LAN device driver from working properly. The alerts reset part of the LAN and
prevent an operating system’s device driver from sending or receiving some LAN
packets.
10. After step 8 (reset attempt), if the reset is unsuccessful, then the CMI continues
sending a message every period. The CMI does not attempt to reboot the system
again without external intervention.
A system that has locked up and can not be restarted with the power button press is
assumed to have broken hardware (bad power supply, short circuit on some bus, etc.),
and is beyond the CMI’s recovery mechanisms.
The following rules/steps apply if the system is in a G0 state and the policy is for the
CMI to not reboot the system after a hardware lockup:
1. Upon detecting the lockup the SECOND_TO_STS bit is set. The CMI sends a
message with the Watchdog (WD) Event status bit set (and any other bits that
must also be set). This message is sent as soon as the lockup is detected, and is
sent with the next (increment) sequence number.
2. After step 1, the CMI sends a message every period until some external
intervention occurs.
3. Rules/steps 4-10 apply if no user intervention (resets, power button presses,
SMBus reset messages) occur after a third timeout of the watchdog timer. If the
intervention occurs before the third timeout, then jump to step11.
4. After step 3 (third timeout), if the user does a Power Button Override, the system
goes to an S5 state. The CMI continues sending messages at this point.
5. After step 4 (power button override), if the user presses the power button again,
the system must wake to an S0 state and the CPU must start executing the BIOS.
6. If step 5 (power button press) is successful in waking the system, the CMI
continues sending messages until the BIOS clears the SECOND_TO_STS bit.
It is important the BIOS clears the SECOND_TO_STS bit, as the alerts interfere with the
LAN device driver from working properly. The alerts reset part of the LAN and would
prevent an operating system’s device driver from sending or receiving some messages.
7. If step 5 (power button press) is unsuccessful in waking the system, the CMI
continues sending messages. The CMI does not attempt to reboot the system again
until some external intervention occurs (reset, power failure, etc.).
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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