EP80579 Datasheet, PDF (365/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
14.2.1.5
MCERR Enabling Registers
An additional entry to the matrix of error signaling paths is the MCERR (machine check
error) enabling register. In addition to the SERR, SMI, and SCI enabling registers, the
MCERR enabling register allows the occurrence of an error to result in the MCERR#
signal to be asserted on the front side bus. Machine check error is asserted to indicate
an unrecoverable error, which is not a bus protocol violation.
14.2.1.6 Error Escalation Register
Since all error bits in the error registers are fully configurable, meaning that a given
error can be configured to go to any of the four messaging methods, no global error
escalation mechanism is required. Although, the errors occurrence is accumulated in
the global FERR/NERR registers, all error messaging is initiated from the units
themselves, and not from a central location.
14.2.1.7
Error Masking
A new feature being added for CMI is the concept of an error masking register. Each
unit has a mask register, which blocks the recognition/logging/reporting of each specific
error type. Since the error will not be recognized when the corresponding mask bit is
set, no error messages can be generated. This feature allows intelligent software to
ignore specific error types during critical areas of code, where it does not want to be
informed of errors that it will create, without ignoring other error types that it doesn’t
expect to happen. These mask bits will default to unmasked, and must be set by
software or BIOS to take effect.
14.2.1.7.1 Locking DRAM Address and Syndrome on Errors
The first pair of error logging registers for CE (correctable errors) DRAM_SECF_ADD
and DRAM_SECF_SYNDROME are locked when bit 0 of the DRAM_FERR is set. The
second pair of error logging registers for CE (correctable errors) DRAM_SECN_ADD and
DRAM_SECN_SYNDROME are locked when bit 0 of the DRAM_NERR is set. These pairs
of two registers will retain their value even if new CE’s are found. This allows the first
(and possibly next) error to be captured and held instead of retaining the last.
Corrected data errors as a result of either demand reads or scrubber-initiated traffic
will be reflected in these error registers.
The logging register for UE (uncorrectable errors), DRAM_DED_ADD is locked when bit
1 of the DRAM_FERR or DRAM_NERR is set. This register holds the address of
uncorrectable errors on data reads not initiated by the scrubber for either periodic or
demand scrubbing.
The logging register for Scrub detected errors, DRAM_SCRUB_ADD should be locked
when bit 2 of the DRAM_FERR or DRAM_NERR is set. This register holds the address for
scrubber-initiated transactions for either demand or periodic memory scrubbing.
When the FERR/NERR registers are cleared the logging registers are free to update
their contents until such time that either of these FERR/NERR registers again lock.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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