EP80579 Datasheet, PDF (973/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
• At the end of the frame, the USB Error Interrupt bit is set in the HC status register.
If the CRC/Time out interrupt is enabled in the Interrupt Enable register, a hardware
interrupt will be signaled to the system.
25.10.2.2 Interrupt on Completion
Transfer Descriptors contain a bit that can be set to cause an interrupt on their
completion. The completion of the transaction associated with that block causes the
USB Interrupt bit in the HC Status Register to be set at the end of the frame in which
the transfer completed. When a TD is encountered with the IOC bit set to 1, the IOC bit
in the HC Status register is set to 1 at the end of the frame if the active bit in the TD is
set to 0 (even if it was set to 0 when initially read).
If the IOC Enable bit of Interrupt Enable register (bit 2 of I/O offset 04h) is set, a
hardware interrupt is signaled to the system. This status bit is set whether the TD
completes successfully, or because of errors. If the completion is because of errors, the
USB Error bit in the HC status register is also set.
25.10.2.3 Short Packet Detect
A transfer set is a collection of data which requires more than 1 USB transaction to
completely move the data across the USB. An example might be a large print file which
requires numerous TDs in multiple frames to completely transfer the data. Reception of
a data packet that is less than the endpoint’s Maximum Packet size during Control, Bulk
or Interrupt transfers signals the completion of the transfer set, even if there are active
TDs remaining for this transfer set. Setting the SPD bit in a TD indicates to the HC to
set the USB Interrupt bit in the HC status register at the end of the frame in which this
event occurs. This feature streamlines the processing of input on these transfer types.
If the Short Packet Interrupt Enable bit in the Interrupt Enable register is set, a
hardware interrupt is signaled to the system at the end of the frame where the event
occurred.
25.10.2.4 Serial Bus Babble
When a device transmits on the USB for a time greater than its assigned Maximum
Length, it is said to be babbling. This error results in the Active bit in the TD being
cleared to 0 and the Stalled and Babble bits being set to one. The C_ERR field is not
decremented for a babble. The USB Error Interrupt bit in the HC Status register is set
to 1 at the end of the frame. A hardware interrupt is signaled to the system.
If an EOF babble was caused by the CMI (due to incorrect schedule for instance), the
CMI will force a bit stuff error followed by an EOP and the start of the next frame.
25.10.2.5 Stalled
This event indicates that a device/endpoint returned a STALL handshake during a
transaction or that the transaction ended in an error condition. The TDs Stalled bit is
set and the Active bit is cleared. Reception of a STALL does not decrement the error
counter. A hardware interrupt is signaled to the system.
25.10.2.6 Data Buffer Error
This event indicates that an overrun of incoming data or a under-run of outgoing data
has occurred for this transaction. This would generally be caused by the CMI not being
able to access required data buffers in memory within necessary latency requirements.
Either of these conditions will cause the C_ERR field of the TD to be decremented.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
973