EP80579 Datasheet, PDF (1392/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Selection between the various configurations is programmable via the MAC Extended
Device Control Register (CTRL_EXT.LINK_MODE bits).
TGMII/MII interface used to communicate between the MAC and he RGMII/RMII gasket
supports 10/100/1000 Mbps operation, with both half- and full-duplex operation at 10/
100 Mbps, and full-duplex operation at 1000 Mbps.
Note:
The GbE MAC is optimized for full-duplex operation in 1000 Mbps mode. Half-duplex
1000 Mbps operation is not supported.
37.5.8.1
MAC/PHY GMII/MII Interface
The GbE MAC communicates through a GMII/MII interface which may be configured for
either 1000 Mbps operation (GMII) or 10/100 Mbps (MII) mode of operation. For proper
network operation, both the internal MAC and the external PHY must be properly
configured to identical speed & duplex settings. Additionally, the translators may need
to be configured in the “CTRL_AUX – Auxiliary Device Control/Status Register”. All MAC
configuration is performed using device control registers mapped into system memory.
The PHY will either auto-negotiate the link with the link partner’s PHY at the other end
of the copper line, or will be forced into it’s configuration by software.
37.5.8.1.1
GMII - 1000 Mbps Operation
During 1000Mbps operation, the MAC/PHY communication occurs via an interface
utilizing a pair of 8-bit buses operating at 125 MHz and accompanied by a handful of
additional clocks and/or qualifiers. This signaling (GMII mode) includes the following
communication:
CRS (carrier sense): Carrier sense is detected by the PHY and indicates activity
on the cable, either incoming or outgoing. This signal is driven by the PHY to the
MAC to enable the MAC to generate link status-change alerts, and suspend transmit
/ ignore receive symbols when no link is present.
COL (collision detection): Collision detection is performed by the PHY, signaled
to the MAC upon detection of a collision on the medium, and remains asserted
while the collision condition persists. For half-duplex operation, COL indicates
detection of simultaneous transmission and reception. Since collisions do not occur
between full-duplex transceivers, the GbE MAC ignores any errant collision-
signaling when in full-duplex mode.
TX_ER (transmit code error): This signaling is used by the MAC to indicate
carrier extension and IPG during packet bursts to the PHY, as well as to force
propagation of transmit errors. Note that the GbE will not transmit error codes.
TX_EN (transmit enable): This signal is asserted from the MAC to the PHY while
transmitting, and used to indicate when the MAC is presenting frame data on the
GMII interface to the PHY for transmission. The MAC asserts TX_EN synchronously
with the first byte of the preamble, and it remains asserted until the final data byte
in a frame, deasserted after the final byte.
GTX _CLK (transmit data clock): In GMII mode, the MAC provides a 125 MHz
transmit clock to the PHY accompanying any transmit data.
TX_DATA (transmit data): Data is transmitted from the MAC to PHY in 8-bit
quantities at 125 MHz when in GMII mode.
RX_CLK (receive clock): In GMII mode, receive data provided from the PHY to
the MAC is accompanied by a 125 MHz receive clock.
RX_DATA (receive data): Data received by the PHY is transferred to the MAC in
8-bit quantities at 125 MHz in GMII mode.
RX_ER (receive error): Receive errors are detected by the PHY and signaled to
the MAC. Receive errors may include link coding errors, or any other error detected
by the PHY. If receive errors are signaled during packet reception, the MAC can be
configured to either receive or drop these packets.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1392
August 2009
Order Number: 320066-003US