EP80579 Datasheet, PDF (1624/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
calculate the path delay from its master. Every sent Delay_Req packet sent by the slave
is time stamped and kept. With the value received from the master with
Delay_Response packet the slave can now calculate the path delay from the master to
the slave.
The implementation of this protocol is typically distributed between hardware and
software.
The HW responsibilities are:
• Identify the packets that require time stamping.
• Time stamp the packets on both RX and TX paths.
• Store the time stamp value for SW.
• Keep the system time in HW and give a time adjustment service to the SW.
• Maintain auxiliary features related to the system time.
The SW responsibilities are:
• BMC protocol execution which means defining the node state (master or slave) and
selection of the master clock if in slave state.
• Read time stamps from HW and generate PTP packets.
• Calculate the time offset and adjust the system time using HW mechanism for that.
• Enable configuration and usage of the auxiliary features.
41.5.1.2.1 Protocol for Ordinary and Boundary Clocks
The synchronization protocol flow and the offset calculation for an ordinary or boundary
clock model are described in Figure 41-3.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1624
August 2009
Order Number: 320066-003US