EP80579 Datasheet, PDF (1740/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 48-8. DDR2 Interface Signals (Sheet 2 of 2)
Signal Name
IO Type
DDR_DQS[8:0]
SSTL_18
DDR_DQS[8:0]# SSTL_18
DDR_CKE[1:0]
SSTL_18
DDR_ODT0
SSTL_18
DDR_ODT1
SSTL_18
DDR_RCOMPX
Analog
DDR_CRES[2:0] Analog
DDR_DRVCRES
Analog
DDR_SLEWCRES Analog
TOTAL
Direction
Ball
Count
I/O
9
I/O
9
O
2
I/O
1
I/O
1
I
1
I/O
3
I/O
1
I/O
1
144
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
BSC
BSC
BSC
BSC
BSC
DDR Channel Data Strobes (Differential): The
positive side of the data strobe. Each data
strobe is used to strobe a set of four or eight
data signals (depending on whether x4 or x8
DRAM devices are used).
DDR Channel Data Strobes (Differential): The
negative side of the data strobe (see
D_DQS[8:0]).
DDR Channel Clock Enable: Independent per-
DIMM-slot clock enables used by the controller
during the initialization sequence.
DDR Compensation: On-die termination
configuration.
DDR Compensation: On-die termination
configuration.
DDR Compensation: CMD/CK/ADD pin slewrate
control.
DDR Compensation: Resistive compensation I/
O's
DDR Compensation
DDR Compensation: DQ/DQS/DM pin slewrate
control.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1740
August 2009
Order Number: 320066-003US