EP80579 Datasheet, PDF (417/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.33 Offset CAh: REMAPOFFSET - Remap Offset Register
This register contains the difference between the REMAPBASE and TOLM.Note: This
register should not be enabled since the IA-32 core only supports 32-bit addressing.
Table 16-35. Offset CAh: REMAPOFFSET - Remap Offset Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: CAh
Offset End: CBh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 10
09 : 00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
REMAPOFFST
Remap Offset: This register contains the difference
between the REMAPBASE and TOLM. This register value
corresponds to address bits 35:26. It is used to translate
the physical FSB address to the system memory address
for accesses to the remap region.
Bit Reset
Value
00h
000h
Bit Access
RW
16.1.1.34 Offset CCh: TOM - Top Of Memory Register
This register contains the effective size of memory. The value in this register hides any
DIMMs that can’t be directly addressed. BIOS determines the memory size reported to
the OS using this register.
Table 16-36. Offset CCh: TOM - Top Of Memory Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: CCh
Offset End: CDh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 9
08 : 00
Bit Acronym
Bit Description
Sticky
Reserved
TOM
Reserved
Top of Memory: This register reflects the effective size of
memory. These bits correspond to address bits 35:27.
(128 Mbyte granularity) Bits 26:00 are assumed to be 0.
Bit Reset
Value
00h
000h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
417