EP80579 Datasheet, PDF (1508/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6.6
ECOL – Excessive Collisions Count Register
When 16 or more collisions have occurred on a packet, this register increments,
regardless of the value of collision threshold. If collision threshold is set below 16, this
counter won't increment. This register will only increment if transmits are enabled and
the device is in half-duplex mode.
Table 37-84. ECOL: Excessive Collisions Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 4018h
Offset End: 401Bh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 4018h
Offset End: 401Bh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 4018h
Offset End: 401Bh
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
ECOL
Number of packets with more than 16 collisions
Sticky
Bit Reset
Value
0h
Bit Access
RC
37.6.6.7
MCC – Multiple Collision Count Register
This register counts the number of times that a transmit encountered more than one
collision but less than 16. This register will only increment if transmits are enabled and
the device is in half-duplex mode.
Table 37-85. MCC: Multiple Collision Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 401Ch
Offset End: 401Fh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 401Ch
Offset End: 401Fh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 401Ch
Offset End: 401Fh
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
MCC
Number of times a successful transmit encountered
multiple collisions.
Sticky
Bit Reset
Value
Bit Access
0h
RC
Intel^® EP80579 Integrated Processor Product Line Datasheet
1508
August 2009
Order Number: 320066-003US